Test Circuit for Flash Memory and Logic Chip Testing
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Solution Overview
Problem
The increasing complexity and cost of testing LSI chips, particularly due to the varied specifications and control methods of flash memories from different vendors, result in lengthy and costly testing processes, as existing test circuits are not adaptable to diverse flash memory models and vendors.
Innovation Solution
A test circuit that can read and execute a test sequence transmitted from an external tester, generate memory control signals specific to nonvolatile memories, and output test results, allowing for efficient testing of flash memories with different specifications by incorporating a command buffer and external interface circuit, and operating according to the SPI standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential testing of logic chip and memory chip is performed using existing test circuits, then testing completeness is ensured, but testing time increases significantly
Solution Approach 1:
The test circuit is segmented into independent components: a logic chip test circuit and a memory chip test circuit. Each circuit can operate independently and simultaneously on its respective chip, enabling parallel testing without interference. This segmentation allows both chips to be tested at the same time rather than sequentially, significantly reducing total testing time while maintaining complete test coverage for both components.
2Measurement precision
If flash memories from different vendors and models are tested using fixed test sequences, then testing accuracy is maintained, but adaptability decreases
Solution Approach 1:
The test circuit incorporates a command buffer that can be dynamically configured with different test sequences and parameters. Rather than using fixed, vendor-specific test sequences, the circuit allows dynamic loading and adjustment of test commands to match the specific requirements of different flash memory vendors and models. This dynamic adaptability maintains testing accuracy for each specific memory type while enabling broad compatibility across multiple vendors and models.
Data Source
AI summary
An efficient test for a flash memory combined with a logic chip and incorporated in a semiconductor integrated device can be executed.A logic chip combined with a rewritable nonvolatile memory and incorporated in a semiconductor integrated device is provided with a test circuit. The test circuit reads a programmable test sequence transmitted from an external tester and stored, generates a memory control signal specific to the nonvolatile memory in accordance with a product ID read on the basis of the test sequence, executes a test in which the generated memory control signal is outputted to the nonvolatile memory, and outputs, to the tester, a test result based on a value outputted from the nonvolatile memory in response to the memory control signal.