Flash Memory Test Isolation Logic Bank With Parallel Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flash memory testing methods face inefficiencies such as limited access and comparison capabilities, serial testing requirements, and the need for specialized equipment, which hinder effective testing and reliability verification, especially in high-reliability applications like automotive systems.
Innovation Solution
An embedded memory test controller within an integrated circuit that provides a programmable interface for parallel testing of flash memory arrays, allowing concurrent access and comparison of multiple bits, independent of system architecture and external test equipment, and enabling self-test capabilities during the IC's lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional flash memory testing methods are used, then testing can be performed with existing equipment, but test time is excessive and parallelism is insufficient
Solution Approach 1:
The memory array is divided into multiple banks, with each bank independently testable through dedicated test interfaces. This segmentation enables parallel testing of multiple banks simultaneously, increasing overall test throughput and reducing total test time while maintaining compatibility with existing test equipment
Solution Approach 2:
The patent introduces a bank select mechanism that adds a new dimension to the testing architecture, allowing sequential access to different memory banks through dedicated interfaces. This dimensional addition enables parallelism without requiring fundamental changes to the underlying memory cell structure or existing test methodologies
2Device complexity
If memory mapping portions of flash to different busses and clock domains is done to decrease address space, then address space is reduced, but access and comparison gaps are created
Solution Approach 1:
The test controller is designed with universal interfaces that can access memory banks regardless of their mapping to different busses or clock domains. The isolation logic provides a unified access path that transcends the underlying architectural divisions, enabling consistent read/write operations across all memory regions without being constrained by bus or clock domain boundaries
3Device complexity
If serial testing is performed to simplify test architecture, then architecture is simpler, but testing efficiency is reduced
Solution Approach 1:
The test architecture is segmented into multiple independent test interfaces, each capable of independently testing a specific memory bank. This segmentation maintains relative architectural simplicity while enabling parallel operation of multiple test interfaces, thereby improving testing efficiency without introducing complex interdependencies between test channels
4Measurement precision
If specialized test equipment is used to achieve thorough testing, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The memory system incorporates self-test capabilities through integrated test controllers and isolation logic that enable thorough defect detection using standard test equipment. The self-service mechanism includes built-in test patterns, comparison logic, and isolation control that perform comprehensive testing without requiring specialized external equipment, thereby maintaining high measurement precision while reducing device complexity and test cost
Data Source
AI summary
An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.