System-Level Flash Memory Test Method for NAND Defect Screening
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Solution Overview
Problem
The lack of a system-level test method for NAND flash memory makes it difficult to perform large-scale screening and testing, hindering the identification of defect rates and hidden issues, as existing methods rely on chip-level and driver-level comparisons which are not scalable or comprehensive.
Innovation Solution
A system-level test method utilizing a test device with a partition mirror storage system and a file storage system, where an original mirror is pre-stored, and verification files with pre-set characters are used to perform simultaneous partition mirror data checks and file data checks, with a test flag file and parameter management to ensure efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip-level and driver-level comparison methods are used for testing NAND flash memory, then existing testing approaches can be maintained, but large-scale screening and testing cannot be performed and defect rates cannot be accurately identified
Solution Approach 1:
The testing system is segmented into multiple independent test modules: partition mirror data check module, file data check module, and parameter management module. Each module performs specific testing functions independently, enabling large-scale screening while maintaining accurate defect identification through systematic division of testing tasks.
Solution Approach 2:
The system performs preliminary actions by pre-storing original mirrors in the partition mirror storage system and pre-storing verification files with pre-set characters in the file storage system before actual testing. This preparation enables efficient large-scale testing without repeated data acquisition, improving both productivity and testing reliability.
2Adaptability or versatility
If existing NAND flash memory lacks a system-level test method, then manufacturer-specific platforms can be used, but comprehensive testing and defect rate identification become difficult
Solution Approach 1:
The testing system is designed with universal functionality that can test various aspects of NAND flash memory including partition mirror data integrity, file data integrity, and parameter verification. The system accommodates different storage configurations and can be applied across multiple manufacturer platforms, achieving both universality and comprehensive defect detection capability.
Solution Approach 2:
The system introduces intermediary components including the partition mirror storage system, file storage system, and test flag file as mediators between the testing process and the NAND flash memory being tested. These intermediaries enable standardized, comprehensive testing that can identify defect rates accurately while maintaining adaptability across different memory configurations.
3Reliability
If comprehensive system-level testing is implemented, then defect identification capability is improved, but test complexity and time consumption increase
Solution Approach 1:
The system performs preliminary actions by pre-storing original mirrors and verification files before actual testing begins. This preparation eliminates the need for repeated data acquisition during testing, significantly reducing test time while maintaining comprehensive defect identification capability through systematic testing of all partitions and files.
Solution Approach 2:
The testing system maintains continuous useful action by systematically iterating through all partitions and files without interruption. The parameter management module continuously tracks test progress and results, enabling comprehensive defect identification through continuous testing while optimizing time consumption through efficient sequential processing of test data.
Data Source
AI summary
The present invention relates to the technical field of integrated chips, and more particularly, to a system-level test method for a flash memory. The method comprises: step S1, providing a test flag file, and storing a test number parameter in the test flag file; step S2, determining whether a value of the test number parameter reaches a pre-set value; if not, turning to step S3; if yes, ending and counting a verification result; step S3, performing one partition mirror data check on all partitions of the flash memory, and performing one file data check on a current system file of the flash memory; and step S4, restarting a test device, subtracting one from the value of the test number parameter, and returning to step S2.