Flash Memory Secure Test Mode Entry via Cryptographic Signature
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Solution Overview
Problem
Existing memory devices lack secure access control mechanisms for test modes, allowing unauthorized access and misuse during manufacturing testing and the operational life of Flash memory arrays.
Innovation Solution
Implementing an access management architecture using cryptographic algorithms, such as Secure HASH or MAC functions, to ensure only authorized users can access specific test modes by calculating and comparing internal and user-provided signatures, with mechanisms for data freshness to prevent replay attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If test mode access is opened without authentication, then ease of operation is improved, but security and reliability deteriorate due to unauthorized access
Solution Approach 1:
The patent introduces an authentication intermediary mechanism that mediates between the test mode entry request and the actual test mode access. The authentication unit acts as a mediator that verifies user credentials before allowing access to test modes, thus maintaining security while enabling legitimate access. This resolves the contradiction by adding a security layer without completely blocking access paths.
Solution Approach 2:
The patent implements preliminary authentication actions before allowing test mode access. The authentication unit performs verification of user credentials, signatures, or keys before the actual test mode is activated. This preliminary security check ensures that only authorized users can access test modes, resolving the security concern while maintaining operational accessibility for legitimate users.
2Reliability
If cryptographic authentication is implemented, then security and reliability are improved, but device complexity increases due to additional authentication mechanisms
Solution Approach 1:
The authentication unit is designed to perform multiple functions: it can verify different types of authentication credentials (signatures, keys, certificates), support multiple test mode access levels, and integrate with existing memory device operations. This multi-functionality reduces the need for separate dedicated security components, thereby limiting the increase in device complexity while maintaining strong security.
Solution Approach 2:
The patent merges the authentication functionality with the existing memory device architecture by integrating the authentication unit into the control logic and utilizing existing data paths and registers. This consolidation approach avoids adding completely separate security subsystems, thus improving security without proportionally increasing device complexity.
3Reliability
If multiple authentication levels are implemented, then security is improved by preventing unauthorized access, but ease of operation deteriorates due to complex access procedures
Solution Approach 1:
The authentication unit dynamically adapts its verification requirements based on the requested test mode and user credentials. Different authentication levels are applied selectively rather than uniformly, allowing simpler authentication for less sensitive operations and stronger authentication for critical test modes. This dynamic approach maintains security while improving ease of operation for legitimate use cases.
Solution Approach 2:
The patent applies different authentication requirements to different test modes and access scenarios based on their security sensitivity. Critical test modes require stronger authentication, while less sensitive modes allow simpler access. This localized quality approach ensures security is strengthened where needed without unnecessarily complicating all access procedures.
Data Source
AI summary
The present disclosure relates to a memory device comprising:an array of memory cells; andan access management architecture providing a secure access to a test mode of the array of memory cells,the access management architecture comprising:a register group comprising data identifying the memory device;a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness;a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature;a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells.The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.