Dynamic Read Count Threshold Adjustment for Flash Memory Reliability
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Solution Overview
Problem
The challenge in flash memory storage devices is setting an appropriate read count threshold to prevent read disturb, as stringent thresholds lead to processing waste and loose thresholds result in data loss, while existing methods fail to adaptively adjust based on actual usage conditions.
Innovation Solution
A memory control method that dynamically adjusts the read count threshold for physical erasing units by monitoring error bit amounts and voltage distribution variations, using models like SVM or RNN to predict and compare voltage distributions, thereby determining the need for refresh operations and recalculating thresholds based on usage parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a more stringent read count threshold is adopted to prevent read disturb, then data reliability is improved, but processing cost increases
Solution Approach 1:
The patent implements dynamic adjustment of read count thresholds based on actual memory cell conditions. Instead of using a fixed stringent threshold for all physical erasing units, the system monitors error bit amounts and voltage distribution variations in real-time, and adjusts thresholds adaptively. This allows the system to maintain high reliability when needed while avoiding unnecessary processing costs when conditions permit, thus resolving the contradiction between data reliability and processing cost.
Solution Approach 2:
The patent changes the parameter of read count threshold from a fixed value to a dynamically adjustable value based on monitored conditions. By detecting error bit amounts and voltage distribution variations, the system modifies the threshold parameter according to actual memory cell states. This parameter change enables the system to optimize between reliability and processing cost by applying stringent thresholds only when necessary.
2Productivity
If a relatively loose read count threshold is adopted to reduce processing cost, then processing efficiency is improved, but data reliability deteriorates
Solution Approach 1:
The system dynamically adjusts read count thresholds based on monitored error bit amounts and voltage distribution variations. When memory cells are in good condition, looser thresholds are applied to improve processing efficiency. When degradation is detected, thresholds are tightened to maintain reliability. This dynamic approach resolves the contradiction by allowing the system to operate efficiently when safe and conservatively when needed.
Solution Approach 2:
The patent implements a feedback mechanism that continuously monitors error bit amounts and voltage distribution variations in physical erasing units. This feedback information is used to adjust read count thresholds adaptively. The feedback loop enables the system to maintain optimal balance between processing efficiency and data reliability by responding to actual memory cell conditions rather than using fixed thresholds.
3Device complexity
If fixed read count thresholds are used to simplify control, then device complexity is reduced, but adaptability to usage conditions deteriorates
Solution Approach 1:
The patent transitions from static fixed thresholds to dynamic adaptive thresholds that respond to actual usage conditions. The system monitors error bit amounts and voltage distribution variations and adjusts thresholds accordingly. This dynamic approach significantly improves adaptability to different usage conditions while the automated nature of the adjustment keeps control complexity manageable.
Solution Approach 2:
The system performs self-adjustment of read count thresholds based on its own monitored conditions. The memory control circuit automatically detects error patterns and voltage variations, then autonomously modifies thresholds without requiring external intervention or complex control algorithms. This self-service approach enhances adaptability while keeping the control mechanism relatively simple.
Data Source
AI summary
A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: setting preset read count thresholds corresponding to physical erasing units respectively; in a background operation, in response to a read count of a first physical erasing unit in the physical erasing units being greater than its corresponding preset read count threshold, reading word lines in the first physical erasing unit to obtain first error bit amounts; determining whether a refresh operation needs to be performed on the first physical erasing unit according to first error bit amounts; in response to no need to perform the refresh operation on the first physical erasing unit, selecting a first word line with the largest first error bit amount in the word lines, and detecting a voltage distribution variation of the first word line; and calculating a new read count threshold of the first physical erasing unit according to the voltage distribution variation.