Flash Memory Read Threshold Tuning for ECC Recovery Delays
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Solution Overview
Problem
The performance of SSD storage systems is significantly degraded due to exponentially increasing read delays when attempting to recover data with bit errors exceeding the error correction capability of conventional ECC codes, leading to loss of stored information.
Innovation Solution
A method and apparatus that adjust the read voltage threshold incrementally and utilize joint data from multiple reads to adjust confidence levels for improved error correction decoding, reducing read delays and enhancing the success rate of error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Read Retry mechanism is used to adjust read voltage threshold multiple times to recover data with bit errors exceeding ECC capability, then data recovery success rate is improved, but read delay increases exponentially from microseconds to milliseconds
Solution Approach 1:
The patent applies preliminary action by performing multiple reads of the same flash memory page and storing the results before attempting error correction. By pre-fetching and caching multiple versions of the data with different read voltage thresholds, the system prepares multiple candidate solutions in advance, allowing the error correction algorithm to select from pre-prepared options rather than performing sequential retries during the critical path, thus reducing read delay while maintaining high data recovery success rate
Solution Approach 2:
The patent implements dynamics by making the read voltage threshold adjustable and variable during the error correction process. The system dynamically selects different read voltage thresholds for multiple reads of the same page, and the error correction algorithm dynamically chooses which read result to use based on error patterns. This dynamic adaptation allows the system to optimize for both data recovery success and read speed without being constrained by a fixed read voltage threshold
2Device complexity
If conventional ECC codes are used with limited error correction capability, then device complexity is reduced, but data recovery capability fails when bit errors exceed the correction threshold
Solution Approach 1:
The patent merges multiple conventional ECC decoding attempts with different read voltage thresholds into a unified error correction process. By combining the results of multiple reads (each with potentially different error patterns) and applying error correction algorithms to the combined data, the system achieves enhanced error correction capability without requiring a completely new complex ECC code design. The merging of multiple data versions allows the system to overcome limitations of individual ECC codes
Solution Approach 2:
The patent applies parameter changes by varying the read voltage threshold parameter across multiple reads of the same flash memory page. This parameter variation causes different bits to be read correctly in different attempts, effectively transforming a static error correction problem into a dynamic one where the system can leverage multiple parameter settings to recover data that would be unrecoverable with a single fixed parameter setting
Data Source
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AI summary
The present invention provides a flash memory error correction method and apparatus. The method includes: determining a first data bit in data obtained by reading a flash memory page by using an (n+1)th read voltage threshold and data obtained by reading the flash memory page by using an mth read voltage threshold, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page by using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page by using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page by using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page by using the (n+1)th read voltage threshold. Two pieces of data obtained by reading a same flash memory page twice are jointly used, and a confidence level of a data bit corresponding to different data is reduced, so as to effectively improve a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.