Flash Memory Toggle Bit Monitoring via Cache Exclusion

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Solution Overview

Problem

Conventional flash memory manipulation processes are inefficient due to the need to deactivate cache memory to detect completion, leading to prolonged processing times, especially when dealing with sector-level operations like deletion or writing, where the entire sector must be erased or rewritten.

Innovation Solution

A method where a processing device with a buffer establishes a non-cacheable exclusion range that includes the monitoring range, allowing the buffer to remain active for fast execution while reliably monitoring the toggle bit for completion, thus enabling early detection of manipulation completion and reducing processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cache memory is deactivated to monitor the toggle bit, then the completion of manipulation can be detected, but the processing time increases significantly

Engineering Contradiction:
Improvedetection reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory address space is segmented into cacheable and non-cacheable ranges. The monitoring range (containing the toggle bit) is excluded from the buffer/cacheable area, while the rest of the memory range can be cached. This allows simultaneous caching for speed and direct monitoring for reliability without deactivating the entire cache.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The monitoring range is extracted from the cacheable memory range and placed in a separate non-cacheable exclusion range. This extraction allows the toggle bit to be monitored directly from the flash memory without reading it into the cache, eliminating the need to deactivate the cache while maintaining both fast processing and reliable detection.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If the entire sector is deleted before rewriting, then the flash memory can be re-written, but the processing time increases due to the erasure operation

Engineering Contradiction:
ImproverewritabilityVSAvoidprocessing time
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The exclusion range is established in advance before the manipulation operation begins. This preliminary configuration ensures that the monitoring range is already separated from the cacheable area, allowing the manipulation to proceed with full cache availability while maintaining reliable completion detection through direct monitoring of the toggle bit.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7346743B2Excluding a toggle bit from the range of cacheable addresses in a flash memory
Publication Date: 2008.03.18 FRANCOTYP POSTALIA AG & CO KG
  • US7346743B2 patent drawing
  • US7346743B2 patent drawing
  • US7346743B2 patent drawing

AI summary

In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first memory range of the data memory, the processing device monitors a monitoring range of the first memory range, the state progression of which allowing the conclusion of the manipulation of the first memory range to be detected. A processing device with a buffer is used, into which buffer the data are read from the data memory. A sub-range of the data memory is established as a first exclusion range of the data memory. The first exclusion range not being read into the buffer. The first exclusion range is established in an establishing step preceding the manipulation step. The exclusion range includes the monitoring range.