Flash Memory Transfer Unit Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data management schemes for flash memory are complex due to non-standard sized data blocks and filler bits, which increase metadata control requirements and complicate data tracking across memory arrays, dies, planes, and pages, while also inefficiently managing error correction as error rates degrade over the memory's operational life.
Innovation Solution
A novel data management scheme that writes data in fixed-sized code words with adjustable payload and parity data, grouped into fixed-sized transfer units, using a transfer unit bit map to identify requested data for retrieval and a transfer unit available bit map to manage data availability, allowing for dynamic adjustment of error correction strength based on the memory's error rate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-standard sized data blocks and filler bits are used in flash memory, then data can be stored in the memory, but the metadata control requirements increase and data tracking becomes complicated
Solution Approach 1:
The patent divides the flash memory into standard-sized blocks with uniform structure, eliminating the need for complex metadata to track non-standard blocks. Each block is segmented into fixed pages and words, creating a regular address space that simplifies control requirements while maintaining storage capacity.
Solution Approach 2:
The patent changes the block size parameter from non-standard to standard sizes, and introduces a wear counter parameter to track erase cycles. This parameterization allows simplified metadata management while preserving the ability to manage data storage capacity effectively.
2Reliability
If error correction strength is increased to handle degraded memory performance, then reliability improves, but processing time and computational resources increase
Solution Approach 1:
The patent implements dynamic error correction by adjusting the strength of ECC based on the wear counter value. For freshly written data with low wear counts, weaker (faster) correction is used. For data with high wear counts indicating degraded memory, stronger (slower) correction is applied. This dynamic adaptation resolves the contradiction between reliability and processing time.
Solution Approach 2:
The patent uses wear counter information as feedback to determine the appropriate error correction strength. The wear counter provides continuous feedback about memory degradation, allowing the system to adjust ECC parameters accordingly, thereby optimizing the balance between reliability and processing time.
3Measurement precision
If more metadata is stored to track data across memory arrays, dies, planes, and pages, then data tracking accuracy improves, but the available memory for user data decreases
Solution Approach 1:
The patent segments the memory hierarchy into standardized blocks, pages, and words with fixed sizes. This segmentation creates a regular address space that reduces the amount of metadata needed for tracking, as the structure is predictable and uniform across all memory elements, thereby preserving more space for user data.
Solution Approach 2:
The patent changes the metadata approach from tracking individual non-standard blocks to tracking standard blocks with uniform parameters. This parameterization reduces metadata volume while maintaining accurate data tracking through the standardized memory hierarchy.
4Productivity
If fixed-sized transfer units are used instead of variable sized blocks, then data management efficiency improves, but flexibility in data placement is reduced
Solution Approach 1:
The patent segments data into fixed-sized transfer units that align with the standardized block structure. This segmentation enables efficient data management through uniform handling of fixed units while maintaining the ability to place data anywhere in the memory space through virtual address mapping, thus preserving flexibility.
Solution Approach 2:
The patent introduces a virtual address space as an intermediary between the fixed-sized physical blocks and the variable-sized logical data structures. This intermediary layer provides flexibility in data placement while maintaining the efficiency benefits of fixed-sized transfer units at the physical level.
Data Source
AI summary
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.