Peripheral Transistor Gate Floating for Flash Memory Reliability
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Solution Overview
Problem
In NAND type flash memory, the high voltage applied during erase operations can lead to destruction of gate insulating films in charge/discharge and select transistors, which are often formed in the same well as memory cells to reduce chip area, posing a risk to the integrity of these components.
Innovation Solution
A nonvolatile semiconductor storage device configuration that includes a gate driving circuit to maintain the gate of peripheral transistors in a floating state during erase operations, preventing high voltage application to their insulating films and thus reducing the risk of damage, while allowing the gate potential to follow the well potential, thereby protecting the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If charge/discharge transistors and select transistors are formed in the same well as memory cells to reduce chip area, then chip area is reduced, but gate insulating films of these transistors may be destroyed by high voltage during erase operations
Solution Approach 1:
The patent segments the well into two distinct regions: a first well region for memory cells and a second well region for charge/discharge transistors and select transistors. This spatial segmentation allows different voltage conditions to be applied to each region independently, protecting the gate insulating films of peripheral transistors while maintaining compact area utilization.
Solution Approach 2:
The patent applies different voltage characteristics to different regions of the well. The first well region (memory cells) can withstand high voltage during erase operations, while the second well region (peripheral transistors) is protected from high voltage. This local differentiation of voltage tolerance resolves the contradiction between area reduction and reliability.
2Productivity
If high voltage is applied to memory cells during erase operations, then erase operation is enabled, but gate insulating films of peripheral transistors in the same well may be destroyed
Solution Approach 1:
By segmenting the well into first and second well regions, the patent enables high voltage to be applied selectively to the first well region (memory cells) during erase operations while isolating the second well region (peripheral transistors) from high voltage exposure, thus enabling erase functionality without causing damage.
Solution Approach 2:
The patent introduces an intermediate structural arrangement where peripheral transistors are positioned in a separate well region that acts as a buffer or mediator between the high voltage environment of memory cells and the sensitive gate insulating films of charge/discharge transistors, protecting them from harmful high voltage effects.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor.