Flash Memory Transistor Layout for Withstand Voltage
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Solution Overview
Problem
The reduction in chip area of flash memory devices makes it challenging to secure a high withstand voltage for transistors, leading to potential breakdown and increased leak current during erase operations, which complicates the boosting of erase voltage and affects the reliability of memory transistors.
Innovation Solution
The layout of connection transistors within the bit line connection transistor portion is optimized, with transistors aligned in specific directions and configurations to increase the distance between the drain diffusion layer and the p-type impurity well, enhancing the withstand voltage and reducing leak current, thereby ensuring reliable operation under high erase voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If chip area is reduced to meet miniaturization requirements, then device integration density is improved, but transistor withstand voltage deteriorates leading to breakdown and increased leak current
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the transistor structure. Specifically, a first impurity concentration zone with higher concentration is formed near the channel region, while a second impurity concentration zone with lower concentration extends toward the drain. This non-uniform doping profile locally enhances the withstand voltage capability at critical regions without requiring overall device enlargement, thus resolving the contradiction between chip miniaturization and transistor reliability.
2Power
If high erase voltage is applied to memory cell array, then data erasing function is achieved, but peripheral circuit may be destroyed due to voltage breakdown
Solution Approach 1:
The patent introduces connection transistors as intermediary protective elements between the memory cell array and peripheral circuits. These connection transistors are specifically designed with enhanced withstand voltage capabilities through optimized impurity concentration profiles. They act as voltage buffers that can safely handle high erase voltages during memory erasing operations, preventing voltage spikes from reaching and damaging the peripheral circuit while still enabling effective data erasure.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a connecting portion having a first region between a memory cell array and a sense amplifier portion and including transistors in the first region, one of the transistors having a first terminal electrically connected to a certain memory cell and a second terminal electrically connected to the sense amplifier portion, the connecting portion including: a first transistor group configured from transistors aligned in a first direction, the first direction being as their channel width direction; and a second transistor group configured from transistors aligned in a second direction intersecting the first direction, the second direction being as their channel width direction, and one of the first terminals of the transistors of the second transistor group being disposed more inside of the first region than one of the second terminals of the transistors of the second transistor group.