Self-Aligned Trap Layer Patterning for Flash Memory Scaling

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Solution Overview

Problem

The existing self-aligned semiconductor memory device fabrication processes face challenges in scaling due to the limitations imposed by the upwardly extending wings of the charge trapping layers, which restrict the close placement of memory cells, impacting memory capacity and cost-effectiveness.

Innovation Solution

A method involving the deposition of a non-conformal film over the charge trapping layer, followed by a dry or wet etch process to create a void and separate the trapping structures, allowing for closer placement of memory cells by forming a pinch-off or narrow channel region, and subsequent oxidation to isolate the trapping layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a self-aligned process with upwardly extending wings is used, then alignment precision is improved, but memory cell spacing increases reducing scalability

Engineering Contradiction:
Improvealignment precisionVSAvoidmemory cell spacing
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent segments the charge trapping layer into isolated regions between core cells by etching away the nitride material in the trenches. This segmentation removes the upwardly extending wings that previously occupied space, allowing memory cells to be placed closer together while maintaining self-alignment benefits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the problematic upwardly extending wing structures from the charge trapping layer by selectively etching the nitride material in the trench regions. This removal eliminates the space occupation that limited scalability while preserving the self-aligned charge trapping functionality over the core cells.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If memory cells are placed closer together, then memory capacity increases, but short channel effect worsens

Engineering Contradiction:
Improvememory capacityVSAvoidshort channel effect
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent addresses the short channel effect by modifying the vertical structure of the charge trapping layer. By removing the upwardly extending wings and creating a more confined vertical profile, the electric field distribution is improved, mitigating short channel effects even as cells are placed closer together horizontally to increase capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Stability of the object's composition

If a conformal film is used, then film uniformity is improved, but void formation is prevented reducing etch selectivity

Engineering Contradiction:
Improvefilm uniformityVSAvoidetch selectivity
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent inverts the conventional approach by using a non-conformal film deposition process that intentionally creates voids in the trench regions. This inversion of the conformal deposition principle allows the film to be thinner or absent in specific areas, enabling selective etching of the nitride charge trapping layer in trenches while preserving it over core cells.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables superior scalability by allowing core cells to be placed closer together, reducing the drain voltage and mitigating the short channel effect, thereby enhancing memory capacity and reducing costs.

Implementation Method 1

a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

A dry or wet etch or a combination of dry and wet etch is performed on the non-conformal film and the thin oxide on the trapping layer

Methodology Applied
Scientific EffectPlasma Etching: Plasma

Implementation Method 3

A dry or wet etch or a combination of dry and wet etch is performed on the non-conformal film and the thin oxide on the trapping layer on the STI oxide

Methodology Applied
Scientific EffectChemical Etching: Oxidation

Implementation Method 4

subsequent oxidation to isolate the trapping layers

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS8035153B2Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications
Publication Date: 2011.10.11 MONTEREY RESEARCH LLC
  • US8035153B2 patent drawing
  • US8035153B2 patent drawing
  • US8035153B2 patent drawing

AI summary

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.