Flash Memory Error Correction Using ADC and Trellis Coding
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Solution Overview
Problem
Multi-level solid state non-volatile memory systems face increased errors due to reduced signal distance between voltage levels, leading to reduced noise margin and increased susceptibility to erroneous readouts, especially in low-level signals.
Innovation Solution
Implementing a system with an analog-to-digital converter and error correction code techniques that encode and decode data to increase the number of digital levels, utilizing modulation and encoding schemes adapted to the voltage constraints of solid state non-volatile memories, and employing convolutional codes and trellis coded modulation to enhance the signal-to-noise ratio and coding gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are used to increase storage density, then storage capacity increases, but signal distance between voltage levels decreases leading to increased errors
Solution Approach 1:
The patent applies parameter changes by using an analog-to-digital converter to transform the analog voltage levels from multi-level memory cells into a greater number of digital levels. This conversion changes the parameter of signal representation from limited voltage distinctions to expanded digital level distinctions, thereby increasing storage capacity while maintaining reliability through enhanced signal discrimination capability
Solution Approach 2:
The analog-to-digital converter serves as an intermediary component between the multi-level memory cells and the digital processing system. It mediates the transition by receiving analog signals with reduced voltage distance and converting them into digital signals with increased level distinction, thus resolving the contradiction between increased storage density and maintained signal reliability
2Quantity of substance
If the number of quantization levels is increased to store more bits per cell, then storage capacity increases, but noise margin decreases making the system more prone to erroneous readouts
Solution Approach 1:
The patent replaces the direct analog voltage sensing approach with an analog-to-digital conversion mechanism. Instead of relying on the physical voltage distance between levels for error resistance, the system converts analog voltages into digital levels that provide enhanced noise immunity through the inherent properties of digital representation and processing
Solution Approach 2:
The system changes the parameter of signal representation from analog voltage levels with narrow margins to digital levels with expanded distinction. This parameter transformation allows the system to maintain higher bits-per-cell capacity while achieving improved noise margin through the greater number of distinguishable digital levels
Data Source
AI summary
A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal.