Flash Memory Trench Isolation for Transient Program Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, including flash memory devices, are scaled smaller, transient program disturb (TPD) becomes a significant challenge due to secondary electron injection during programming, affecting the memory window of dual bit devices.
Innovation Solution
The fabrication of flash memory devices involves forming a trench between gate stacks and implanting impurity doped regions to block secondary electrons, with a conductive material filling the trench to reduce resistance and enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled smaller to increase density, then device density is improved, but transient program disturb increases due to secondary electron injection affecting adjacent cells
Solution Approach 1:
The patent introduces intermediate structures (trenches filled with conductive material or doped regions) between adjacent memory cells to segment the continuous substrate into isolated regions. This segmentation prevents secondary electrons generated in one cell from diffusing to adjacent cells, thereby reducing transient program disturb while maintaining high device density through close spacing of cells.
Solution Approach 2:
The patent employs intermediate structures (conductive fill material or doped regions) as mediators between adjacent memory cells. These intermediaries act as barriers that block the harmful diffusion of secondary electrons while allowing the cells to remain in close proximity, thus resolving the contradiction between high density and reduced program disturb.
2Object-affected harmful factors
If intermediate structures are added between gate stacks to block secondary electrons, then transient program disturb is reduced, but device complexity increases
Solution Approach 1:
The patent combines the formation of intermediate structures with existing fabrication steps. The trenches are formed using the same etch processes as the gate stacks, and the conductive fill material or doped regions are integrated into the existing bit line formation process. This merging of steps adds minimal complexity while effectively reducing transient program disturb.
Solution Approach 2:
The intermediate structures serve dual purposes: they block secondary electron diffusion to reduce program disturb, and they provide additional bit line routing functionality. This self-service approach allows the structures to perform multiple functions, reducing the need for separate components and minimizing the increase in device complexity.
3Productivity
If conductive material is used to fill trenches between gate stacks, then bit line resistance is reduced and programming efficiency is enhanced, but manufacturing complexity increases
Solution Approach 1:
The conductive fill material in the trenches serves multiple functions: it provides low-resistance bit line routing for efficient programming, and it acts as a barrier to secondary electron diffusion. This multi-functionality allows the structure to improve programming efficiency while the added manufacturing complexity is offset by the elimination of separate structures that would otherwise be needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces transient program disturb, allowing for the scaling of memory devices while maintaining or improving performance by blocking secondary electron diffusion and reducing bit line resistance.
Implementation Method 1
Secondary electrons resulting from the secondary impact ionization diffuse to the disturbed cell 34 below gate 26
Implementation Method 2
A conductor is formed within the trench extending along the length of the substrate
Implementation Method 3
A dual bit memory cell 34 is programmed utilizing a hot electron injection technique. More specifically, programming of the first bit 28 of memory cell 34 comprises injecting electrons into the charge trapping layer 20
Implementation Method 4
The voltage on the control gate 26 inverts a channel region 36 while the bias accelerates electrons from bit line 14 into the channel region 36
Implementation Method 5
hot holes generated during programming of first bit 28 of memory cell 32 have a secondary impact ionization below bit line 16
Data Source
AI summary
Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.