Flash Memory Trim Information Storage for Operational Efficiency

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Solution Overview

Problem

Flash memory devices lack efficient optimization of operational time periods for programming, erasing, and reading modes, leading to suboptimal performance.

Innovation Solution

Incorporating a memory cell array with trim information and control logic that adjusts operational time periods based on received trim information during power-up, optimizing programming, erasing, and reading modes by controlling clock signals and operational cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fixed operational time periods are used for programming, erasing, and reading modes, then the device structure is simple, but the operational efficiency and performance are suboptimal

Engineering Contradiction:

Improveoperational efficiencyVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by storing optimized operational time periods in trim information during manufacturing, then automatically utilizing this pre-optimized data during device operation without requiring complex real-time adjustment mechanisms

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by enabling the operational time periods to be adjustable based on trim information stored in the memory cell array, allowing the device to adapt its timing parameters dynamically rather than using fixed values

Inventive Principle:

Principle #15Dynamics

2Reliability

If operational time periods are optimized for each mode, then the performance is improved, but the device complexity increases due to additional control logic

Engineering Contradiction:

ImproveperformanceVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the control logic for optimizing operational time periods with the existing memory cell array structure by storing trim information directly in the array, eliminating the need for separate external control circuits

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The device performs self-optimization by automatically reading trim information from the memory cell array during power-up and using it to configure operational parameters without requiring external intervention or complex manual setup

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS7821836B2Flash memory device and method in which trim information is stored in memory cell array

Publication Date: 2010.10.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode, and to optimize operational time periods of the programming, erasing, and reading modes in accordance with the trim information.