Flash Memory Triple Well Electrical Isolation
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Solution Overview
Problem
Existing flash memory devices face challenges in maintaining electrical isolation between the cell array region and peripheral regions, particularly during high-voltage operations, which can lead to voltage and signal losses and potential damage to peripheral circuit devices.
Innovation Solution
The implementation of a triple well structure in both the cell array and peripheral regions, where each well is configured to provide specific conductivity types and doping concentrations, enhances electrical isolation and reduces voltage losses by using a combination of p-wells and n-wells with varying doping concentrations and depths to accommodate different types of transistors and switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a simple well structure is used in flash memory devices, then the device complexity is reduced and manufacturing is easier, but electrical isolation between cell array region and peripheral regions deteriorates, leading to voltage and signal losses
Solution Approach 1:
The patent divides the semiconductor substrate into multiple conductivity type regions (p-wells and n-wells) to segment the cell array region from peripheral regions. This segmentation creates electrical isolation barriers that prevent voltage and signal losses while maintaining manageable manufacturing processes through systematic well formation.
Solution Approach 2:
The patent applies different well structures (p-wells in cell array region, n-wells in peripheral regions) to different local areas based on their specific electrical isolation requirements. This local quality approach ensures optimal electrical isolation in each region without unnecessarily complicating the entire device structure.
2Adaptability or versatility
If high-voltage operations are performed in flash memory devices, then the functional capability is improved, but the risk of damage to peripheral circuit devices increases due to poor electrical isolation
Solution Approach 1:
The patent introduces intermediary well structures (p-wells and n-wells) that act as buffer zones between the cell array region capable of high-voltage operations and the peripheral circuit regions. These intermediary wells absorb and isolate high-voltage effects, protecting peripheral circuits from damage while preserving high-voltage functionality where needed.
3Reliability
If a triple well structure with multiple doping concentrations and depths is implemented, then electrical isolation and insulation characteristics are enhanced, but the device complexity and manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary well formation actions by establishing the triple well structure (p-wells and n-wells with different doping concentrations and depths) before final device assembly. This preliminary action ensures that electrical isolation is built into the foundation of the device, simplifying subsequent manufacturing steps and reducing precision requirements for later processes.
Data Source
AI summary
A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.