Flash Memory Programming Using TSG Discharge Pulses to Reduce Fail Bits
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Solution Overview
Problem
Flash memory devices face issues with increased fail bit counts due to charge accumulation during suspend operations, particularly in verify phases, affecting unselected channels and overall device performance.
Innovation Solution
A method involving applying discharge pulses to unselected top select gates and controlling gate voltages to manage charge accumulation, including a merged discharge pulse that overlaps with program and verify phases to optimize timing and reduce fail bit counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If suspend operations are performed during verify phase, then device can handle multiple operations concurrently, but charge accumulation increases fail bit count
Solution Approach 1:
The patent extracts the charge accumulation problem from the suspend operation by applying a discharge pulse to the unselected top select gate. This discharge pulse removes the accumulated charge that would otherwise cause fail bits, thereby separating the beneficial suspend functionality from its harmful side effect.
Solution Approach 2:
The patent applies a discharge pulse before the suspend operation completes to prevent charge accumulation from reaching levels that would cause fail bits. This preliminary anti-action counteracts the potential harm before it manifests, allowing suspend operations to proceed safely.
2Reliability
If discharge pulse is applied to unselected top select gate, then charge accumulation is reduced, but additional voltage pulses increase operation complexity
Solution Approach 1:
The patent merges the discharge pulse with existing voltage pulses in the program and verify phases. By overlapping the discharge pulse timing with necessary select gate activations, the patent reduces charge accumulation without requiring completely separate control sequences, thereby limiting the increase in operational complexity.
Solution Approach 2:
The unselected top select gate serves multiple functions: it is activated during normal program/verify operations for channel selection, and it receives discharge pulses to remove charge accumulation. This multi-functionality reduces the need for additional dedicated discharge structures, limiting complexity increase.
3Loss of time
If merged discharge pulse overlaps program and verify phases, then timing efficiency is improved, but precise voltage control becomes more difficult
Solution Approach 1:
The patent uses periodic program and verify phases with regularly timed discharge pulses overlaid. This periodic structure provides predictable timing patterns that simplify control logic, allowing merged discharge pulses to be timed efficiently without excessive complexity in voltage control.
Solution Approach 2:
The patent adjusts voltage parameters (amplitude, duration, timing) of the discharge pulse to optimize its effect during merged phases. By carefully controlling these parameters, the patent achieves effective charge removal during overlapping phases while maintaining manageable control complexity through parameter optimization rather than structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method efficiently programs and verifies memory cells, reducing fail bit counts and improving suspend and resume operations in flash memory devices.
Implementation Method 1
when suspending during a verify phase, increased charge accumulation on the memory channel can increase a fail bit count (FBC) of the memory device
Data Source
AI summary
A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.