Flash Memory Tunnel Oxide Edge Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of nonvolatile semiconductor memory devices, the tunnel oxide layer often thins at the edge portions due to concentrated stress, leading to deteriorated electrical characteristics and reduced reliability, as the alignment errors between the floating gate and active region result in uneven thickness and increased electron leakage.
Innovation Solution
The implementation of compensation members on the edge portions of the insulation layer, formed by oxidizing the lower edge portions of the conductive layer, ensures a uniform thickness of the tunnel oxide layer, preventing thinning and enhancing the coupling ratio by extending the edge portions of the insulation layer and conductive layer to the isolation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the tunnel oxide layer is formed on the active region using conventional photolithography, then the manufacturing process is simple, but the alignment error between the floating gate and active region increases, causing the tunnel oxide layer thickness to become non-uniform at edge portions
Solution Approach 1:
The patent forms preliminary isolation regions with protruded upper portions before forming the tunnel oxide layer. These protruded portions serve as pre-positioned structures that guide the subsequent formation of the floating gate and ensure proper alignment, preventing the alignment errors that would otherwise occur with conventional photolithography methods
Solution Approach 2:
The patent introduces compensation members as intermediary structures formed on the edge portions of the tunnel oxide layer. These compensation members act as mediators that locally adjust and compensate for thickness variations in the tunnel oxide layer, ensuring uniform effective thickness despite variations in the underlying active region geometry
2Ease of manufacture
If the tunnel oxide layer thickness is reduced at edge portions due to stress concentration, then the manufacturing process is easier, but the electrical characteristics deteriorate due to concentrated Fowler-Nordheim tunneling and increased electron leakage
Solution Approach 1:
The patent applies local quality by forming compensation members specifically at the edge portions of the tunnel oxide layer where thickness variations and stress concentration occur. These compensation members provide localized thickness compensation only where needed, without affecting the central regions, thereby maintaining uniform effective tunnel oxide thickness at critical edge areas while preserving the overall device structure
Solution Approach 2:
The patent implements preliminary anti-action by pre-forming the compensation members on the edge portions of the tunnel oxide layer before subsequent processing steps. This preliminary compensation counteracts the potential harmful effects of stress-induced thinning and alignment errors that would otherwise occur during later manufacturing steps, preventing electrical characteristic deterioration before it happens
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves the electrical characteristics and reliability of the semiconductor device by preventing Fowler-Nordheim tunneling concentration and leakage current, while enhancing the coupling ratio through the use of compensation members and a conductive layer with a width greater than the active region.
Implementation Method 1
formed by oxidizing the lower edge portions of the conductive layer
Implementation Method 2
Fowler-Nordheim (F-N) tunneling through the tunnel oxide layer
Data Source
AI summary
In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.


