Flash Memory Programming Speed via Selective Verify Skipping

The patent applies local quality by differentiating the treatment of different memory cells within the same array. Specifically, it identifies and separates first memory cells requiring verify operations from second memory cells where verify operations can be skipped. This localized differentiation allows the system to maintain high accuracy for critical cells while optimizing speed for less critical cells, thereby resolving the contradiction between overall accuracy and programming time.

The patent implements partial action by selectively performing program verify operations only on a subset of memory cells (first memory cells) rather than all memory cells. The control logic determines which cells require verification based on their programming state, applying verify operations partially to those that need it most, while skipping them for cells where the programming outcome is sufficiently certain, thus reducing total verification time while maintaining acceptable accuracy.

The patent employs feedback mechanisms through the control logic that monitors programming conditions and determines selectively which memory cells require verify operations. The control logic uses feedback from the programming process state, voltage increments, and memory cell characteristics to make intelligent decisions about verify operation skipping, ensuring that accuracy is not compromised while maximizing speed improvements.

The patent applies parameter changes by modifying the programming parameters (voltage increments, program loop counts) dynamically based on memory cell characteristics and programming stage. By adjusting these parameters selectively for different memory cell groups, the system optimizes both speed and accuracy - using fewer verify operations for cells with favorable parameters while maintaining verification for cells requiring higher precision, thus resolving the speed-accuracy contradiction.