Flash Memory Verify Voltage Adjustment for Endurance

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Solution Overview

Problem

Flash memory devices face reliability issues due to the detrapping effect, which causes electrons and holes to be released from the floating gate, leading to accuracy degradation and reduced endurance, especially in multi-level cells after repeated programming and erasing cycles.

Innovation Solution

A method is introduced to determine an additional verifying voltage based on the number of programming/erasing cycles, conducting additional verifying and programming operations to compensate for threshold voltage variations, thereby maintaining data accuracy and extending the memory block's lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If flash memory cells undergo repeated programming and erasing cycles, then data storage capacity is maintained, but threshold voltage accuracy degrades due to the detrapping effect

Engineering Contradiction:

ImproveenduranceVSAvoidthreshold voltage accuracy

Core Design Contradiction:

Duration of action of moving objectVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing an additional verifying operation with an elevated verifying voltage before finalizing the programmed state. This advance verification compensates for anticipated threshold voltage shifts due to detrapping, ensuring long-term data accuracy without requiring multiple re-programming cycles.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the result of the additional verifying operation to determine whether additional programming is needed. If cells fail the elevated voltage verification, the system provides feedback to perform additional programming, creating a closed-loop control that maintains threshold voltage accuracy despite aging effects.

Inventive Principle:

Principle #23Feedback

2Measurement precision

If additional verifying operations with elevated voltages are performed, then data accuracy is improved, but processing time increases

Engineering Contradiction:

Improvedata accuracyVSAvoidprocessing time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by performing the additional verifying operation selectively based on programming age. Instead of verifying all cells with elevated voltage at all times, the system applies the additional verification primarily to older memory blocks that have undergone more programming cycles and are more susceptible to detrapping, reducing overall processing time while maintaining accuracy where needed.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If verify voltage is increased to compensate for detrapping effect, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidverification process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the verifying voltage adaptive rather than static. The verification process dynamically adjusts the voltage level based on the programming age of the memory block, using elevated voltages for older blocks and standard voltages for newer blocks. This dynamic approach maintains high reliability while avoiding unnecessary complexity in the verification process.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7986560B2Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same

Publication Date: 2011.07.26 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.