Flash Memory Virtual Address Space Management
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Solution Overview
Problem
In flash memory systems, inconsistencies between logical and physical page sizes due to compression or ECC expansion lead to inefficient storage, with increased unused areas and management complexity when logical pages cannot extend over physical pages, resulting in reduced storage efficiency and increased management information size.
Innovation Solution
A flash memory storage device with a controller that manages a virtual address space, allowing logical pages to be stored across multiple physical blocks without adhering to physical page boundaries, using a page mapping table to record unused areas, thereby minimizing management information and enhancing storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If logical pages are constrained to fit within single physical pages, then management complexity is reduced, but storage efficiency deteriorates due to increased unused areas
Solution Approach 1:
The patent segments the mapping relationship by introducing a virtual address space that is divided into virtual blocks, which are then mapped to physical blocks. This segmentation allows logical pages to span multiple physical pages without increasing the complexity of management, as the system only needs to track virtual-to-physical block mappings rather than detailed page-level mappings.
Solution Approach 2:
The patent introduces a virtual address space as an intermediary layer between the logical address space and the physical address space. This virtual address space acts as a mediator that abstracts the complexity of physical page boundaries, allowing logical pages to naturally span across physical pages while maintaining simple management through virtual-to-physical block mapping.
2Quantity of substance
If logical pages are allowed to extend over multiple physical pages, then storage efficiency is improved, but management information size increases
Solution Approach 1:
The patent segments the address space hierarchy into logical pages, virtual blocks, and physical blocks. By managing mappings at the virtual block level rather than the logical page level, the system enables logical pages to span multiple physical pages while keeping management information size constant, as each virtual block maps to a contiguous range of physical blocks.
Solution Approach 2:
The patent adds a virtual address space dimension between the logical and physical address spaces. This additional dimensional layer allows the system to manage complex spanning relationships indirectly through virtual-to-physical block mappings, avoiding the need to track detailed page-level mapping information.
3Reliability
If compression or ECC expansion is applied, then data protection or density is improved, but inconsistency between logical and physical page sizes increases storage inefficiency
Solution Approach 1:
The patent uses the virtual address space as an intermediary that absorbs the size differences caused by compression or ECC expansion. The virtual block size can be configured independently of the physical page size, allowing the system to accommodate variable data sizes while maintaining efficient physical page utilization and simple block-level mapping management.
Data Source
AI summary
The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing data, wherein the device divides and manages a logical storage space provided to a higher level device in logical page units, and manages a virtual address space which is a linear address space to which multiple physical blocks of the semiconductor device are mapped. The storage device uses a page mapping table managing a correspondence between a logical page and an address in the virtual address space, and a virtual address configuration information managing a correspondence between an area in the virtual address space and a physical block, in order to manage the correspondence between the respective logical pages and storage areas of the semiconductor device.