Flash Memory Readout Using Viterbi Decoding Against Cell Interference
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Solution Overview
Problem
As the geometry of flash memory devices is reduced, inter-signal interference (ISI) between neighboring memory cells affects the accuracy of data read operations, necessitating an error-correcting logic or algorithm to ensure reliable data retrieval.
Innovation Solution
Implementing a Viterbi algorithm or its variant to process raw data from flash memory devices, constructing a trellis graph of all possible data states, and determining a data path with minimum error to correct data read operations, thereby mitigating the impact of inter-signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the geometry of flash memory is reduced to increase storage density, then the storage capacity is improved, but inter-signal interference between neighboring memory cells increases
Solution Approach 1:
The memory array is divided into multiple independently decodable pages, where each page can be read and corrected separately. This segmentation allows the Viterbi algorithm to process smaller units of data with known boundary conditions, reducing the cumulative effect of inter-signal interference across the entire array while maintaining high storage density.
Solution Approach 2:
The Viterbi algorithm performs preliminary error correction on raw data before it is fully processed and stored. By constructing a trellis graph of all possible data states and determining the most likely sequence in advance, the system proactively mitigates inter-signal interference effects before they propagate through subsequent operations.
2Measurement precision
If error-correcting logic is added to mitigate inter-signal interference, then data retrieval accuracy is improved, but device complexity increases
Solution Approach 1:
The Viterbi algorithm acts as an intermediary processing layer between the physical memory cells and the logical data storage system. It receives raw data with potential errors, processes it through the trellis graph to identify the most likely intended sequence, and outputs corrected data. This intermediary approach achieves high retrieval accuracy without requiring fundamental changes to the memory cell structure.
Solution Approach 2:
The patent replaces complex hardware error correction circuits with a software-based Viterbi algorithm implementation. Instead of adding physical error correction logic at the circuit level, the system uses computational algorithms to achieve the same goal, reducing hardware complexity while maintaining or improving correction effectiveness.
3Measurement precision
If the Viterbi algorithm is used to correct data errors, then data retrieval accuracy is improved, but processing time increases
Solution Approach 1:
The Viterbi algorithm processes data in segmented pages rather than entire arrays. By dividing the memory space into smaller independently decodable units with known start and stop patterns, the algorithm reduces the computational complexity and processing time for each correction operation while maintaining overall accuracy across the full storage capacity.
Data Source
AI summary
Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.