Flash Memory Gate Patterns with Void Insulation
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Solution Overview
Problem
As the level of integration in flash memory devices increases, the space between gate patterns narrows, leading to increased interference capacitance and significant cell Vt shift due to charging from neighboring cells, which affects the electrical characteristics of the devices.
Innovation Solution
A method of manufacturing flash memory devices involves forming gate patterns and select transistors over a semiconductor substrate, followed by the creation of a buffer insulating layer, an insulating layer with voids between the gate patterns for cells, and the deposition of a nitride layer, with spacers formed on one side of the select transistors using a spacer etch process to reduce interference capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the level of integration is increased, then the device density is improved, but the interference capacitance between gate patterns increases
Solution Approach 1:
The patent extracts the harmful insulating material from the spaces between gate patterns for cells, creating voids that remove the source of interference capacitance. This allows higher device density without the capacitance penalty that would normally accompany closer gate spacing.
Solution Approach 2:
The patent applies different treatments to different spatial regions: voids are created between gate patterns for cells to reduce capacitance, while insulating layers are maintained between gate patterns for select transistors to enable proper spacer formation. This localized differentiation resolves the capacitance issue without compromising transistor functionality.
2Length of stationary object
If the space between gate patterns is narrowed, then the integration level is improved, but the cell Vt shift becomes profound
Solution Approach 1:
By removing insulating material from between cell gate patterns, the patent eliminates the capacitance coupling that causes Vt shift. This allows narrow gate spacing while maintaining stable threshold voltages, directly resolving the reliability issue.
3Object-affected harmful factors
If voids are formed between gate patterns for cells, then the interference capacitance is reduced, but the etch damage to source and drain lines may occur
Solution Approach 1:
The patent maintains insulating layers between gate patterns for select transistors while creating voids between gate patterns for cells. This localized insulation preservation provides etch protection for source and drain lines during spacer etching, preventing damage while still achieving capacitance reduction where needed.
Solution Approach 2:
The remaining insulating layer between select transistor gates acts as an intermediary protective barrier during etching processes. It shields the underlying source and drain lines from etch damage while allowing the void formation to proceed in other regions for capacitance reduction.
Data Source
AI summary
A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.