Flash Memory Voltage Biasing for Temperature Stability

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Solution Overview

Problem

Flash memory devices experience deterioration in program characteristics due to temperature changes, which affect the injection of charges into floating gates and result in leakage currents in unselected memory cells.

Innovation Solution

A flash memory device comprising a first memory cell, a second memory cell, a row decoder, and a bias generator, where the bias generator adjusts the word line voltage and unselected source line voltage based on ambient temperature to maintain consistent bit line voltage levels, thereby minimizing leakage currents and improving program characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed voltage levels are applied to word lines and source lines, then the device structure remains simple, but program characteristics deteriorate with temperature changes

Engineering Contradiction:
Improveprogram characteristic consistencyVSAvoidvoltage control mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic voltage adjustment by making the word line voltage and unselected source line voltage variable with temperature. The bias generator dynamically changes voltage levels based on detected temperature conditions, transforming fixed voltage control into adaptive voltage control to maintain consistent program characteristics across temperature ranges.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter based on temperature conditions. By adjusting the word line voltage and unselected source line voltage according to temperature variations, the system compensates for temperature-induced threshold voltage shifts in transistors, thereby maintaining reliable program operations without requiring fundamental structural changes.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If standard programming voltages are used, then the programming process is simple, but leakage current increases in unselected memory cells at varying temperatures

Engineering Contradiction:
Improveleakage current controlVSAvoidbias control circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different voltage levels to different line types based on their specific functions and temperature conditions. The word line receives a first voltage level while the unselected source line receives a second voltage level, both adjusted according to temperature. This localized voltage control minimizes leakage current in unselected cells while maintaining simple overall device structure.

Inventive Principle:
Principle #3Local quality

3Reliability

If temperature compensation is implemented, then program characteristics remain consistent, but the control mechanism becomes more complex

Engineering Contradiction:
Improveprogram characteristic stabilityVSAvoidtemperature sensing and voltage adjustment system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the bias generator detects temperature conditions and adjusts the word line voltage and unselected source line voltage accordingly. This closed-loop temperature compensation ensures consistent program characteristics by continuously adapting voltage levels to match actual operating conditions, while keeping the feedback mechanism integrated within the existing bias generation infrastructure.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10636491B2Flash memory device and method of programming the same
Publication Date: 2020.04.28 SAMSUNG ELECTRONICS CO LTD
  • US10636491B2 patent drawing
  • US10636491B2 patent drawing
  • US10636491B2 patent drawing

AI summary

A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.