Flash Memory Voltage Boost Circuit for Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices require specific voltages for programming and erasing operations, leading to high power consumption and operational voltage levels, which are not efficiently managed by existing voltage generation circuits.
Innovation Solution
The flash memory apparatus incorporates pre-charge voltage transmitters and pumping capacitors to boost external pre-charge voltages to programming and erasing control voltages, reducing external power consumption and allowing shared voltage generators across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge-pump circuit or voltage generation circuit is used to provide specific voltages for programming and erasing operations, then the flash memory can perform programming and erasing operations, but the power consumption and operational voltage levels become high
Solution Approach 1:
The patent applies preliminary action by pre-charging the control gate before the actual programming or erasing operation. A pre-charge voltage transmitter charges a pump capacitor to a predetermined voltage level in advance, so that when programming or erasing is needed, the high voltage is already available, reducing the power consumption and time required for voltage generation during the actual operation.
Solution Approach 2:
The patent implements self-service by using the flash memory's own internal pump capacitor and pre-charge voltage transmitter to generate the required high voltages for programming and erasing operations. Instead of relying on external voltage generation circuits, the flash memory device generates its own control voltages, thereby reducing external power consumption and eliminating the need for complex external voltage generation circuits.
2Reliability
If a voltage generation circuit is included in the flash memory, then programming and erasing operations can be performed, but the physical area required for the voltage generation circuitry increases
Solution Approach 1:
The patent merges the voltage generation functionality into the existing flash memory structure by integrating the pre-charge voltage transmitter and pump capacitor with the control gate circuitry. This consolidation eliminates the need for separate external voltage generation circuits, reducing the overall physical area required while maintaining the capability to perform programming and erasing operations.
Solution Approach 2:
The pump capacitor serves multiple functions: it acts as a storage element for the control gate voltage, functions as a voltage amplifier during programming and erasing operations, and can be shared across multiple memory cells. This multi-functionality reduces the need for dedicated voltage generation circuitry for each memory cell, thereby reducing the overall physical area.
3Use of energy by moving object
If external pre-charge voltages are transmitted to control end points and boosted to programming or erasing control voltages, then power consumption from external sources is reduced, but the device complexity increases
Solution Approach 1:
The patent extracts the voltage generation function from external circuits and implements it within the flash memory device itself. By taking out the voltage generation requirement from the external system and incorporating a pre-charge voltage transmitter and pump capacitor internally, the device reduces external power consumption while the added internal components are minimal and integrated into the existing memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution lowers the operational voltage and power consumption of the flash memory apparatus while enabling efficient programming and erasing operations, and reduces the physical area required for the voltage generation circuitry.
Implementation Method 1
The pumping capacitor is coupled between the control end point of the memory cells and a pumping voltage. The pumping voltage is applied to the pumping capacitor during a second period of time, and generates the control voltage for programming at the control end points of the memory cells.
Implementation Method 2
The erasing pumping capacitor is coupled between the erase end point of the memory cells and an erasing pumping voltage. The erasing pumping voltage is applied to the erasing pumping capacitor during a fourth period of time, and generates an erasing control voltage for erasing at the erase end points of the memory cells.
Data Source
AI summary
A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.