Flash Memory Wear and Retention Measurement via Voltage Distribution
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Solution Overview
Problem
Current non-volatile semiconductor flash memory systems face challenges in accurately measuring and predicting memory wear and data retention, as bit error rate (BER) is not a reliable indicator and fails to distinguish between wear, read disturb errors, and data retention loss, leading to inefficient memory management.
Innovation Solution
The system independently measures and predicts memory wear and data retention by analyzing cell voltage distributions, allowing for dynamic adjustments of memory parameters and improved analytics to extend endurance and prevent data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If bit error rate (BER) is used as an indicator for memory wear and data retention, then memory management can be simplified, but measurement precision deteriorates because BER cannot distinguish between wear, read disturb errors, and data retention loss
Solution Approach 1:
The patent segments the unified BER measurement into distinct components by separately measuring wear (through program/erase cycle tracking and voltage distribution analysis) and data retention (through charge loss measurement over time). This segmentation allows each parameter to be measured with appropriate precision while maintaining manageable complexity through dedicated measurement protocols for each parameter type.
Solution Approach 2:
The patent introduces voltage distribution analysis as an intermediary measurement method that bridges the gap between simple BER counting and precise wear/retention differentiation. By measuring the distribution of threshold voltages across memory cells, the system can distinguish between cells degraded by wear versus those experiencing retention loss, providing precise measurement without excessive operational complexity.
2Quantity of substance
If memory cells are scaled to smaller dimensions to increase capacity per unit area, then storage density improves, but reliability deteriorates due to increased cell endurance issues and defect levels
Solution Approach 1:
The patent applies local quality by implementing wear and retention monitoring at the individual block level rather than uniformly across the entire memory device. Each block's voltage distribution and error characteristics are measured and managed independently, allowing the system to identify and retire only the specific blocks that have degraded, thereby maintaining reliability in scaled cells without sacrificing overall storage capacity.
Solution Approach 2:
The patent implements preliminary action by continuously monitoring voltage distributions and measuring wear/retention parameters before memory blocks reach critical failure points. By detecting early signs of degradation through voltage shift analysis and conducting preventive block cycling or data migration, the system maintains reliability in scaled memory cells before defects manifest as actual data loss.
3Productivity
If aggressive programming modes are used to improve performance, then productivity increases, but memory wear accelerates reducing endurance
Solution Approach 1:
The patent applies dynamics by making programming aggressiveness adjustable based on real-time wear measurements. The system can dynamically switch between aggressive programming modes (for high productivity when blocks are fresh) and conservative modes (for extended endurance when wear is detected). Voltage distribution monitoring provides feedback that enables this dynamic adaptation of programming parameters to balance performance and longevity.
Solution Approach 2:
The patent implements parameter changes by adjusting programming voltage levels, pulse widths, and timing based on measured block wear status. When voltage distribution analysis indicates a block has undergone significant program/erase cycling, the system modifies programming parameters to reduce stress on that block, thereby extending overall memory endurance while maintaining acceptable productivity through intelligent parameter adaptation.
Data Source
AI summary
A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.