Flash Memory Voltage Fault Recovery via On-Chip Cache
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Solution Overview
Problem
Non-volatile memory systems, such as flash memory, face data corruption due to voltage faults during write operations, leading to incomplete programming and the need for error messages and host intervention, which increases processing and voltage regulation demands on the host system.
Innovation Solution
A memory device with an on-chip cache and memory controller that retains safe copies of data sectors until they are confirmed written, allowing for safe recovery and writing to the non-volatile memory array only when the voltage is within an acceptable range, thereby avoiding error signals to the host and minimizing host processing demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write interrupt procedure is invoked and an error message is sent to the host when a voltage fault occurs, then data corruption is prevented, but the host processing burden increases and voltage regulation demands are heightened
Solution Approach 1:
The memory controller performs preliminary actions by maintaining safe copies of data sectors in on-chip cache before writing to the non-volatile memory array. When a voltage fault occurs, these pre-retained safe copies enable automatic recovery without requiring host intervention or error messages, thus preventing data corruption while eliminating additional host processing burden
Solution Approach 2:
The memory device implements self-service capability through automatic detection and recovery from voltage faults. The memory controller monitors voltage conditions, retains safe copies in cache, and automatically writes these copies to the memory array when voltage stabilizes, eliminating the need for host involvement in error handling and reducing host processing demands
2Reliability
If safe copies of data sectors are retained in on-chip cache until confirmed written, then data integrity is ensured during voltage faults, but device complexity increases
Solution Approach 1:
The data writing process is segmented into distinct phases: data reception, safe copy retention in on-chip cache, voltage condition monitoring, and confirmation writing to the non-volatile memory array. This segmentation allows the memory controller to manage complexity systematically by handling each phase separately, ensuring data integrity while maintaining controllable device complexity
Solution Approach 2:
The on-chip cache acts as an intermediary between the host interface and the non-volatile memory array. It temporarily stores safe copies of data sectors, enabling the memory controller to decouple the data reception from the actual writing operation. This intermediary mechanism simplifies the overall control logic by providing a buffer that can be managed independently during voltage fault conditions
3Ease of operation
If the memory device automatically recovers from voltage faults without host intervention, then host processing demands are minimized, but the ability to detect and respond to voltage faults becomes more complex
Solution Approach 1:
The memory controller implements feedback mechanisms by continuously monitoring the supplied memory voltage and comparing it against defined voltage ranges. When a voltage fault is detected (voltage outside acceptable range), the controller triggers appropriate responses such as pausing write operations or invoking recovery procedures using safe copies in cache. This automated feedback loop enables voltage fault detection and response without host intervention, minimizing host processing burden while maintaining manageable detection complexity through systematic voltage monitoring
Data Source
AI summary
Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.