3D Flash Memory Voltage Overshoot Prevention
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Solution Overview
Problem
In 3D flash memory devices, parasitic resistance and capacitance differences between word lines lead to overshot program voltages and prolonged setup times, degrading program performance.
Innovation Solution
A programming method that applies a first pass voltage to unselected word lines during a first interval, a second pass voltage higher than the first to unselected word lines during a second interval, and a discharge voltage lower than the program voltage to the selected word line after applying the program voltage, followed by the program voltage during the second interval, to prevent overshot and quicken voltage setup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program voltage is applied to a selected word line in 3D flash memory devices, then memory cells can be programmed, but parasitic resistance and capacitance differences between word lines cause voltage overshot and prolonged setup time
Solution Approach 1:
The patent applies pass voltages to unselected word lines before applying the program voltage to the selected word line. This preliminary action prepares the voltage environment and prevents parasitic coupling effects from causing voltage overshot or prolonged setup time during the actual programming operation.
Solution Approach 2:
The patent applies discharge voltages to the selected word line after the initial program voltage application. This preliminary anti-action counteracts the parasitic capacitance effects that would otherwise cause voltage overshot, by actively discharging excess voltage before it can cause harmful effects.
2Reliability
If a program voltage is applied to a selected word line, then memory cells are programmed, but the setup time is prolonged due to parasitic effects
Solution Approach 1:
Pass voltages are applied to unselected word lines in advance of the program voltage application. This preliminary voltage establishment reduces the time required for the selected word line to reach its target voltage level by pre-configuring the voltage environment and minimizing parasitic coupling delays.
Solution Approach 2:
The patent uses a multi-stage voltage application sequence with distinct time intervals: first applying pass voltages to unselected word lines, then applying the program voltage to the selected word line, and finally applying discharge voltages. This periodic, staged approach optimizes the timing of voltage transitions to reduce overall setup time while maintaining program reliability.
Data Source
AI summary
A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.