Flash Memory Programming Speed Uniformity via Location-Based Voltage Compensation
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Solution Overview
Problem
Conventional flash memory devices experience inconsistent programming and erase speeds due to distributed substrate resistance, leading to non-uniform voltage delivery across memory cells, which affects reliability and performance.
Innovation Solution
A flash memory device employs a programming compensation technique that adjusts voltage levels based on the location of memory cells within the memory array, using a compensation component to provide varying programming voltages to ensure consistent programming speed across all cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional uniform voltage programming is applied to all memory cells, then the programming circuit design is simple, but the programming speed is inconsistent across different wordlines due to distributed substrate resistance
Solution Approach 1:
The patent applies local quality by providing different programming voltage levels to different wordlines based on their specific locations in the memory array. Wordlines closer to the substrate pickup receive lower voltages while those farther away receive higher voltages, compensating for the distributed substrate resistance effects and achieving uniform programming speed across all cells.
Solution Approach 2:
The patent changes the programming voltage parameter dynamically based on wordline position. By adjusting the voltage level according to the distance from the substrate pickup, the system compensates for resistance variations and maintains consistent programming performance throughout the array.
2Productivity
If higher programming voltage is applied to all cells to speed up programming, then programming speed increases, but voltage variation effects are amplified leading to greater non-uniformity
Solution Approach 1:
Instead of uniformly increasing voltage across all wordlines, the patent applies local quality by tailoring the voltage increase to each wordline's position. This ensures that cells experiencing greater resistance effects receive proportionally higher voltages, maintaining uniformity while achieving overall speed improvement.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the programming voltage level based on wordline position rather than applying a fixed voltage. This position-dependent voltage adjustment allows the system to maintain both speed and uniformity.
3Manufacturing precision
If location-based voltage compensation is implemented, then programming speed uniformity improves, but the control mechanism becomes more complex
Solution Approach 1:
The patent implements local quality through a systematic approach where each wordline is assigned a specific voltage level based on its position. This methodical distribution of voltage levels achieves uniform programming while maintaining manageable control complexity through regular patterns.
Solution Approach 2:
The control complexity is managed through parameter changes by using a systematic voltage assignment scheme rather than complex individual control for each cell. The voltage level is adjusted as a function of wordline position, creating a manageable control structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances uniformity in programming speed and reliability by compensating for the effects of distributed substrate resistance, improving the overall performance and cost-effectiveness of the flash memory device without increasing complexity or size.
Implementation Method 1
depending on the position of the wordline in the memory array containing the memory cell, the voltage levels actually received at the memory cell can vary due to distributed resistance of the memory array
Data Source
AI summary
Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.