Flash Memory Voltage Pulse Adjustment for Programming Efficiency
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Solution Overview
Problem
Flash memory devices face inefficiencies in programming and erasing operations due to increasing threshold voltages over multiple program/erase cycles, leading to over-programming or over-erasure issues, as the initial voltage settings become inadequate, requiring excessive pulses to maintain performance.
Innovation Solution
The control logic in the memory device adjusts programming or erase voltage pulses based on the rate of operation by comparing the number of failed bits or bytes to predetermined reference values, incrementing the voltage or pulse duration to optimize programming or erasing efficiency independently of the number of cells to be programmed or erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If initial voltage settings are used for programming and erasing operations, then the device can operate initially, but the threshold voltages increase over multiple program/erase cycles causing over-programming or over-erasure issues and requiring excessive pulses to maintain performance
Solution Approach 1:
The patent applies dynamics by making the voltage pulse characteristics adjustable based on operational conditions. Specifically, the control logic dynamically modifies the amplitude and/or duration of programming and erasing voltage pulses based on the number of pulses already applied to a memory block. This allows the system to adapt to threshold voltage changes over time, maintaining programming accuracy while reducing the total number of pulses needed compared to static voltage approaches.
Solution Approach 2:
The patent implements parameter changes by systematically varying voltage pulse amplitude and duration based on the program/erase cycle count. The control logic adjusts these parameters in response to detected threshold voltage shifts, thereby maintaining optimal programming and erasing performance throughout the device lifecycle without requiring excessive pulses.
2Productivity
If voltage pulses are increased to maintain performance over multiple cycles, then programming and erasing effectiveness is maintained, but the risk of over-programming or over-erasing increases
Solution Approach 1:
The patent employs feedback mechanisms where the control logic monitors the number of programming and erasing pulses applied to each memory block and uses this information to adjust subsequent voltage pulse characteristics. This feedback loop prevents over-programming and over-erasing by reducing voltage amplitude or duration when the pulse count indicates that threshold voltages have shifted, thereby maintaining precision while ensuring effectiveness.
3Productivity
If the number of programming and erasing pulses is reduced, then the operational efficiency improves, but the threshold voltage changes cause programming or erasing failures
Solution Approach 1:
By dynamically adjusting voltage pulse parameters based on the number of pulses already applied, the system maintains high success rates with fewer total pulses. The control logic modifies amplitude and/or duration in response to threshold voltage changes, ensuring each pulse is optimally effective without requiring excessive repetition.
Solution Approach 2:
The system changes voltage pulse parameters (amplitude, duration) based on operational history to maintain programming and erasing success rates while reducing the total number of pulses required, thereby improving operational efficiency without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This adaptive approach ensures efficient programming and erasing by dynamically adjusting voltage steps and pulse widths, maintaining optimal performance across the device's lifecycle without over-programming or over-erasing, thus extending the device's operational efficiency.
Implementation Method 1
the charge is removed through Fowler-Nordheim tunneling of electrons from the floating gate to the channel
Data Source
AI summary
Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A rate at which programming or erasing is proceeding is determined. The programming voltage pulse or the erase voltage pulse is adjusted at least partially in response to the determined rate. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase.


