Flash Memory Voltage Control for Read Disturb Mitigation
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Solution Overview
Problem
NAND flash memory devices experience read disturb issues due to the deterioration of the threshold voltage distribution in the code storage region, leading to reliability concerns and data integrity problems during repeated program/erase cycles.
Innovation Solution
A flash memory device with a memory cell array divided into data and code storage regions, where the control logic adjusts read, program, and verification voltages to differentiate between the two regions, applying lower voltages to non-selected rows in the code storage region and higher voltages to selected rows, thereby reducing read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If read voltage is applied to non-selected word lines during read operations, then read operation can be performed, but threshold voltage distribution deteriorates due to read disturb
Solution Approach 1:
The patent applies different read voltages to different regions: a first read voltage (lower magnitude) is applied to non-selected word lines in the code storage region, while a second read voltage (higher magnitude) is applied to non-selected word lines in the data storage region. This local differentiation reduces read disturb in the code storage region while maintaining read functionality in both regions.
2Productivity
If program voltage is repeatedly applied during program/erase cycles, then data can be programmed, but oxide layer deteriorates and charges are trapped
Solution Approach 1:
The patent applies different program voltage magnitudes to different regions: a first program voltage (lower magnitude) is applied to the code storage region, while a second program voltage (higher magnitude) is applied to the data storage region. This local differentiation reduces stress on the oxide layer in the code storage region during program operations.
3Measurement precision
If verification voltage is applied during program operation, then program accuracy can be verified, but additional voltage stress is applied to the oxide layer
Solution Approach 1:
The patent applies different verification voltage magnitudes to different regions: a first verification voltage (lower magnitude) is applied to the code storage region, while a second verification voltage (higher magnitude) is applied to the data storage region. This local differentiation enables program verification while reducing additional voltage stress on the oxide layer in the code storage region.
Data Source
AI summary
A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation. The control logic controls the voltage generating circuit so that a read voltage provided to the row of the second region is lower than a read voltage provided to a row of the first region.