Flash Memory Data Recovery via Read Voltage Adjustment
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Solution Overview
Problem
Flash memory devices experience data loss due to power abnormalities during upper-bit program operations, which also affect the reliability of the cell distributions formed during lower-bit program operations, leading to unrecoverable data loss.
Innovation Solution
A semiconductor memory device with a memory cell array, an error detector, and a data recoverer that adjusts read reference voltages to identify and recover lost data by determining the logic page of the recovery target data, using a voltage control unit and data transform unit to re-read and write the recovered data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell is used to store more than one bit per memory cell, then storage capacity is improved, but read operation complexity increases due to needing multiple reference voltages
Solution Approach 1:
The patent segments the read reference voltage generation into multiple independent voltage generators (first voltage generator, second voltage generator, third voltage generator) that produce different reference voltages (first reference voltage, second reference voltage, third reference voltage). This segmentation allows the complex multi-level read operation to be divided into manageable stages, where each voltage generator handles a specific portion of the reference voltage requirements, thereby reducing overall system complexity while maintaining high storage capacity.
2Reliability
If power abnormality occurs during upper-bit program operation, then program operation is interrupted, but data loss extends to lower-bit program operation results as well
Solution Approach 1:
The patent performs preliminary actions by completing the lower-bit program operation fully before initiating the upper-bit program operation. The memory cell array is first programmed with lower-bit data to establish a stable baseline distribution, and only after this is complete does the system proceed to upper-bit programming. This sequential approach ensures that if power failure occurs during upper-bit operation, the previously completed lower-bit data remains intact and can be used for data recovery.
Solution Approach 2:
The patent converts the harmful effect of power abnormality into a beneficial recovery mechanism. When power failure is detected during upper-bit programming, the system automatically switches to a recovery mode that uses the intact lower-bit data as a foundation. The data recovery unit leverages the stable lower-bit distribution to reconstruct lost upper-bit information, thereby transforming the partial data loss caused by power failure into a recoverable situation rather than complete data loss.
3Speed
If conventional read operation is performed without voltage adjustment, then read speed is maintained, but data accuracy decreases when cell distribution is abnormal
Solution Approach 1:
The patent implements dynamic read reference voltage adjustment based on the detected cell distribution state. The data recovery unit dynamically selects and applies appropriate reference voltages from the multiple available generators depending on whether the cell distribution is normal or abnormal. This dynamic adaptation allows the system to maintain high read speeds by using optimized voltage levels while simultaneously ensuring data accuracy by selecting the most appropriate reference voltage for the current cell state, resolving the trade-off between speed and precision.
Data Source
AI summary
A semiconductor memory device includes, a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages, an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data, a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data, and a page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array.