Flash Memory Block Allocation for Performance and Wear Balancing

Solution Overview

Problem

Flash memory storage devices exhibit varying performance and resilience based on programming modes (SLC, MLC, TLC, QLC), leading to uneven wear and potential premature failure due to differing P/E cycles, necessitating dynamic allocation strategies to optimize performance and lifespan.

Innovation Solution

A storage system dynamically allocates blocks to high and low resilience portions based on performance parameters and P/E cycle thresholds, using SLC for high resilience and MLC, TLC, or QLC for lower resilience blocks, and rotates allocations to balance wear.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memory uses higher capacity programming modes (MLC, TLC, QLC), then storage capacity increases, but wear resistance decreases due to more P/E cycles

Engineering Contradiction:

Improvestorage capacityVSAvoidwear resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The flash memory device is divided into multiple blocks, with at least two different types of blocks having different programming modes (SLC, MLC, TLC, or QLC). This segmentation allows the system to distribute data across blocks with different durability characteristics, balancing capacity and reliability needs.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different blocks are assigned different programming modes based on local quality requirements. SLC blocks provide higher wear resistance for critical data, while QLC blocks provide maximum capacity for less critical data. This local differentiation optimizes the overall system by matching block characteristics to data importance.

Inventive Principle:

Principle #3Local quality

2Reliability

If flash memory uses SLC programming mode, then wear resistance increases, but storage capacity decreases

Engineering Contradiction:

Improvewear resistanceVSAvoidstorage capacity

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The flash memory device is divided into multiple blocks, with at least two different types of blocks having different programming modes (SLC, MLC, TLC, or QLC). This segmentation allows the system to distribute data across blocks with different durability characteristics, balancing capacity and reliability needs.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different blocks are assigned different programming modes based on local quality requirements. SLC blocks provide higher wear resistance for critical data, while QLC blocks provide maximum capacity for less critical data. This local differentiation optimizes the overall system by matching block characteristics to data importance.

Inventive Principle:

Principle #3Local quality

3Device complexity

If flash memory blocks are statically allocated to specific programming modes, then performance prediction is simplified, but adaptability to varying performance needs decreases

Engineering Contradiction:

Improveperformance prediction simplicityVSAvoidperformance adaptability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The system dynamically determines which blocks are available for allocation and assigns programming modes based on current performance parameters and data characteristics. This dynamic approach allows the system to adapt to changing performance needs while maintaining manageable complexity through automated decision-making.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system monitors performance parameters and uses this feedback to make intelligent allocation decisions. By continuously assessing block availability and performance characteristics, the system adapts its block allocation strategy to optimize both performance prediction accuracy and adaptability to varying needs.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250208776A1Managing flash memory for performance

Publication Date: 2025.06.26 PURE STORAGE INC

AI summary

One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.