Flash Memory Wear Leveling via Dynamic SLC MLC Area Switching
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Solution Overview
Problem
Flash memory devices have a lifespan disparity due to different management methods used in memory blocks, leading to premature expiration of the storage device as a whole, as memory blocks managed using Single Level Cell (SLC) and Multi Level Cell (MLC) methods have varying endurance.
Innovation Solution
A storage device with a memory controller that calculates and compares the wear out ratios of memory areas managed using SLC and MLC methods, alternately programming specific attribute data to ensure both areas expire at nearly the same time, thereby extending the overall lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory blocks are managed using different methods (SLC and MLC) to optimize reliability and capacity, then data storage efficiency is improved, but lifespan disparity occurs between memory areas
Solution Approach 1:
The patent implements dynamic management of memory areas by allowing flexible allocation and switching between SLC and MLC modes based on wear out ratios. The memory controller dynamically adjusts which memory area serves as the active program area versus the standby area, adapting to the actual wear state of each area to balance lifespan utilization.
Solution Approach 2:
The patent changes the operational parameters of memory blocks by switching between different cell types (SLC/MLC) and operational modes (program area/standby area) based on wear out ratios. This parameter change allows the system to optimize both storage capacity and lifespan by adjusting the reliability and capacity characteristics of different memory areas according to their current state.
2Ease of operation
If specific attribute data is always programmed in one designated memory area, then management simplicity is maintained, but lifespan imbalance accelerates device expiration
Solution Approach 1:
The patent implements periodic switching between program area and standby area based on wear out ratio thresholds. When the wear out ratio of the current program area exceeds a predetermined threshold, the system periodically switches roles between memory areas, ensuring that wear is distributed more evenly across all memory blocks over time.
Solution Approach 2:
The patent maintains a standby memory area that is prepared in advance as a backup. When the primary program area approaches its lifespan limit (high wear out ratio), the system can switch to the pre-prepared standby area, preventing data loss and extending the overall device lifespan without requiring complex real-time reallocation.
3Reliability
If memory blocks with high reliability (SLC) are used for important data, then data reliability is improved, but device lifespan is limited by lower reliability blocks (MLC)
Solution Approach 1:
The patent dynamically assigns the roles of program area and standby area based on wear out ratios rather than fixed allocation. This allows SLC-managed memory blocks to serve as the program area when they have lower wear, while MLC-managed blocks serve as standby or program areas when appropriate, optimizing both reliability and lifespan utilization across different cell types.
Solution Approach 2:
The patent aims to equalize the wear out ratios of different memory areas by implementing wear leveling through role switching. By monitoring and comparing wear out ratios across SLC and MLC managed areas, the system distributes wear more uniformly, ensuring that no single area becomes the limiting factor for overall device lifespan.
Data Source
AI summary
A storage device includes a nonvolatile memory device including memory blocks divided into a first memory area and a second memory area; and a memory controller. In the case of programming specific attribute data, the memory controller determines a memory area in which the specific attribute data will be programmed according to a wear out ratio of the first memory area and a wear out ratio of the second memory area. The wear out ratio is a ratio of the current maximum erase count of memory blocks of a memory area with respect to the allowable maximum erase count of the memory area.