Flash Memory Wear-Leveling via Priority Group Allocation

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Solution Overview

Problem

Conventional flash memory devices face durability and reliability issues due to memory block deterioration from repetitive programming and erasing cycles, leading to 'bad blocks' and performance degradation, as wear-leveling methods fail to evenly distribute usage effectively.

Innovation Solution

A memory system with a memory controller that allocates flash memory blocks into high, intermediate, and low priority groups based on erasure counts and error correction data, ensuring even usage distribution and minimizing the difference in usage between blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional linear wear-leveling maps memory blocks and uses each block sequentially, then memory blocks are used uniformly, but system performance deteriorates because some blocks become error-prone over time

Engineering Contradiction:
Improvememory block reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory blocks are segmented into multiple priority groups (first priority, second priority, third priority) based on their error characteristics. This segmentation allows the system to differentiate between healthy blocks and deteriorating blocks, allocating new data strategically to maintain performance while preserving reliable blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different priority levels are assigned to different memory blocks based on their local quality (error susceptibility). Blocks with fewer errors receive higher priority, ensuring that data is preferentially stored in more reliable blocks, thereby maintaining overall system performance while extending the life of deteriorating blocks.

Inventive Principle:
Principle #3Local quality

2Duration of action of stationary object

If memory blocks are reused after a fixed number of erasure cycles, then wear is distributed evenly, but blocks with higher error rates continue to be used causing performance degradation

Engineering Contradiction:
Improvememory block lifespanVSAvoiddata retention reliability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The system continuously monitors error rates in each memory block and uses this feedback to dynamically adjust priority assignments. Blocks exhibiting higher error rates are automatically downgraded to lower priority groups, reducing their usage and preserving them from further wear, while healthy blocks receive more usage.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The priority assignment is not static but dynamic, changing based on the actual condition of each memory block. As blocks deteriorate, their priority changes accordingly, allowing the system to adapt to wear patterns and maintain optimal performance throughout the memory device's lifespan.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If error-prone memory blocks are continued to be used to maximize storage capacity, then more blocks remain available, but the likelihood of rapid wear and failure increases

Engineering Contradiction:
Improveusable memory capacityVSAvoidmemory block durability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system changes the parameter of priority assignment based on error characteristics. By adjusting which blocks receive new data based on their error rates, the system optimizes the balance between available capacity and reliability, ensuring that high-priority blocks (with lower error rates) bear the brunt of new writes while low-priority blocks are preserved.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9251015B2Memory system providing wear-leveling by allocating memory blocks among groups
Publication Date: 2016.02.02 SAMSUNG ELECTRONICS CO LTD
  • US9251015B2 patent drawing
  • US9251015B2 patent drawing
  • US9251015B2 patent drawing

AI summary

Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.