Flash Memory Well Voltage Sharing for Power Reduction

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Solution Overview

Problem

Conventional flash memory devices experience high power consumption during erase operations due to the repeated charging and discharging of erase voltage, especially as integration increases and the number of memory cells grows, leading to longer operation times and increased circuit area.

Innovation Solution

An erase method that applies an erase voltage to one well and discharges it to another electrically coupled well, allowing for simultaneous erase verification and voltage sharing between wells, with selective coupling and decoupling based on verification results to optimize power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the erase voltage is repeatedly charged and discharged to the wells during erase operations, then the erase operation can be completed, but the power consumption increases

Engineering Contradiction:

Improveerase operation completionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent recovers the erase voltage from the first well after erase operation and transfers it to the second well for subsequent erase operations, instead of discarding it to ground. This voltage recovery and reuse mechanism significantly reduces power consumption by avoiding repeated charging from the power supply.

Inventive Principle:

Principle #34Discarding and recovering

Solution Approach 2:

The patent maintains the erase voltage in the system through continuous transfer between wells during multiple erase operations, rather than repeatedly charging and discharging to ground. The voltage is continuously utilized across different wells, eliminating idle discharge cycles and maintaining useful action throughout the erase process.

Inventive Principle:

Principle #20Continuity of useful action

2Loss of time

If the erase voltage is applied to multiple wells simultaneously, then the erase operation time is reduced, but the power consumption increases

Engineering Contradiction:

Improveerase operation timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic erase operations on different wells, transferring the erase voltage from one well to another in sequence. Instead of simultaneously charging multiple wells (which would consume double the power), the system performs periodic single-well erase operations, reducing instantaneous power consumption while completing erasure across all wells over time.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent ensures continuous useful action by immediately transferring the erase voltage from the first well to the second well after the first erase operation completes. This eliminates idle time and ensures the voltage is continuously utilized, achieving fast erase operations without the need for simultaneous high-power charging of multiple wells.

Inventive Principle:

Principle #20Continuity of useful action

3Quantity of substance

If the number of memory cells and blocks is increased to improve storage capacity, then the integration is improved, but the area occupied by the well circuit becomes larger

Engineering Contradiction:

Improvestorage capacityVSAvoidwell circuit area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent makes the first and second wells serve multiple functions: they can be independently used for erase operations, and they can also be used alternately with voltage transfer between them. This multi-functionality allows the system to handle larger storage capacities through multiple wells while keeping each individual well's circuit area manageable, as each well can operate independently or in sequence with others.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces power consumption by reusing the erase voltage and shortening the erase operation time by performing verification and erasure simultaneously, while maintaining efficient charge sharing between wells.

Implementation Method 1

discharging the erase voltage from the one of the wells to the other one of the wells electrically coupled with the one of the wells

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9865358B2Flash memory device and erase method thereof capable of reducing power consumption

Publication Date: 2018.01.09 WINBOND ELECTRONICS CORP

AI summary

Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.