Flash Memory Word Line Width Variation Control via Dummy Layer
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Solution Overview
Problem
Conventional flash memory devices experience variations in word line widths and sidewall layer dimensions due to the proximity effect, leading to degraded electric characteristics and current leakage between bit lines and the semiconductor substrate.
Innovation Solution
Incorporating a dummy layer extending in the width direction of bit lines within the bit-line contact region, which helps in reducing the proximity effect during word line formation and ensures consistent sidewall layer dimensions, thereby minimizing variations in word line widths and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed to form bit lines in the semiconductor substrate, then bit lines are formed to serve as source and drain regions, but the bit lines have higher resistance than metal wiring layers, causing degraded writing and erasing performances
Solution Approach 1:
The patent combines metal wiring layers with lower resistance into the bit-line contact region, merging the low-resistance metal pathways with the high-resistance diffusion layer bit lines. This hybrid structure reduces overall resistance while maintaining the functionality of ion-implanted bit lines as source and drain regions.
Solution Approach 2:
The patent introduces metal wiring layers as intermediary conductive elements between the high-resistance diffusion layer bit lines and the external circuitry. These metal layers act as mediators to reduce the overall resistance impact on writing and erasing operations.
2Area of stationary object
If the bit-line contact region is provided for every several word lines to reduce memory cell area, then area is reduced, but proximity effect causes variations in word line widths and sidewall layer dimensions, degrading electric characteristics
Solution Approach 1:
The patent applies preliminary protective actions by forming the bit-line contact region structure before the proximity effect becomes problematic. The contact region is pre-configured with appropriate dimensions and positioning to compensate for expected proximity effect variations during subsequent processing steps.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the bit-line contact region has specific width and positioning characteristics that differ from regular word line regions. This local differentiation allows optimization for both area reduction and proximity effect mitigation in the contact region specifically.
3Manufacturing precision
If contact holes are formed in the bit-line contact region to connect bit lines with wiring layers, then resistance is reduced, but current leakage occurs between bit lines and the semiconductor substrate
Solution Approach 1:
The patent introduces intermediate insulating structures and carefully positioned contact holes that act as mediators between the bit lines and wiring layers. These intermediate elements provide controlled electrical connection while preventing direct leakage pathways to the semiconductor substrate.
Solution Approach 2:
The patent applies different electrical insulation characteristics to different regions: the bit-line contact region has specific insulating layer configurations that differ from other regions. This local differentiation allows current to flow through intended pathways while blocking leakage paths to the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of the dummy layer effectively reduces variations in word line widths and sidewall layer dimensions, enhancing the electric characteristics of memory cells and preventing current leakage between bit lines and the semiconductor substrate, resulting in improved flash memory performance.
Implementation Method 1
ion implantation is performed to form n-type bit lines 12 in a p-type silicon semiconductor substrate 10
Data Source
AI summary
A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.