Flash Memory Word Line Width Uniformity via Extraction

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Solution Overview

Problem

Conventional flash memory devices experience a proximity effect during the formation of word lines, leading to inconsistent widths, particularly adjacent to bit line contact regions, which affects the properties of transistors and memory cells.

Innovation Solution

A method involving the formation of word lines at predetermined intervals, with a metal plug inserted between two word lines to eliminate a portion of them, ensuring uniformity in word line width and reducing proximity effects, as described by the equation L1≦N×(Lw+Ls)+Ls, where L1 is the distance between word lines, Lw is the word line width, and Ls is the distance between word lines, with N being a natural number.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photoresist exposure is used to form word lines, then word lines can be formed at predetermined intervals, but the proximity effect causes non-uniform word line width especially adjacent to bit line contact regions

Engineering Contradiction:
Improveword line width uniformityVSAvoidproximity effect
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and eliminates specific portions of word lines in bit line contact regions by forming openings through the word line layer, removing the source of proximity effect interference and achieving uniform word line width in remaining regions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary anti-action by pre-forming openings in word line layers before subsequent processing steps, preventing the proximity effect from causing non-uniform width in critical bit line contact regions

Inventive Principle:
Principle #9Preliminary anti-action

2Manufacturing precision

If dummy layer is added to suppress proximity effect, then some uniformity can be achieved, but the dummy layer width is larger than word line width and cannot sufficiently suppress the proximity effect

Engineering Contradiction:
Improveword line width uniformityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Instead of adding dummy layers, the patent extracts and removes problematic word line portions in bit line contact regions, achieving uniformity by elimination rather than addition, thereby reducing structural complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the conventional approach of adding dummy structures to suppress proximity effect, instead removing word line portions to eliminate the proximity effect source, achieving uniformity through subtraction

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If word line width varies adjacent to bit line contact region, then proximity effect is present, but this causes different transistor properties from other transistors in the flash memory

Engineering Contradiction:
Improvetransistor property consistencyVSAvoidword line width uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts and removes word line portions in bit line contact regions where proximity effect would cause width variation, ensuring all transistors experience uniform word line dimensions and maintain consistent electrical properties

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by selectively modifying word line structure only in bit line contact regions where proximity effect occurs, maintaining uniform width in critical areas while preserving overall device functionality

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8304914B2Flash memory device with word lines of uniform width and method for manufacturing thereof
Publication Date: 2012.11.06 MONTEREY RESEARCH LLC
  • US8304914B2 patent drawing
  • US8304914B2 patent drawing
  • US8304914B2 patent drawing

AI summary

A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.