Flash Memory Word Line Voltage Control for Parasitic Capacitance
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Solution Overview
Problem
Flash memory devices experience a decrease in cell current and distortion of cell threshold voltage due to interference effects between adjacent memory cells, particularly when all non-selected word lines are driven with equal voltages during read operations.
Innovation Solution
A flash memory device that includes a word line decoder to identify a selected word line and neighboring non-selected word lines, and a word line driver to apply distinct voltages to these lines, with a higher voltage applied to neighboring non-selected word lines to compensate for line-to-line parasitic capacitance, thereby preventing a decrease in cell current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all non-selected word lines are driven with equal voltages during read operations, then the device operation is simplified, but interference effects occur between adjacent memory cells causing decrease in cell current and distortion of cell threshold voltage
Solution Approach 1:
The patent applies different voltage levels to different groups of word lines based on their spatial relationship to the selected word line. Specifically, neighboring non-selected word lines receive a first voltage level while non-neighboring non-selected word lines receive a second voltage level. This local differentiation reduces parasitic capacitance coupling effects on the selected word line while maintaining simplified control architecture.
2Device complexity
If all non-selected word lines are driven with equal voltages during read operations, then the control architecture is simplified, but distortion of cell threshold voltage occurs due to interference effects
Solution Approach 1:
The patent implements local quality by applying different voltage levels to neighboring versus non-neighboring non-selected word lines. The word line decoder identifies the selected word line and generates control signals that apply a first voltage level to neighboring non-selected word lines and a second voltage level to non-neighboring non-selected word lines, thereby reducing threshold voltage distortion while maintaining control simplicity.
3Reliability
If higher voltage is applied to neighboring non-selected word lines to compensate for parasitic capacitance, then cell current is maintained, but device complexity increases
Solution Approach 1:
The patent segments the non-selected word lines into two distinct groups: neighboring non-selected word lines and non-neighboring non-selected word lines. The word line decoder is configured to identify and apply different voltage levels to each group, with neighboring lines receiving a first voltage level and non-neighboring lines receiving a second voltage level, thereby reducing parasitic capacitance effects while maintaining manageable device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The application of different voltages to selected and neighboring non-selected word lines reduces line-to-line parasitic capacitance, maintaining cell current and preventing distortion of cell threshold voltage, thus enhancing read operation performance.
Implementation Method 1
line-to-line parasitic capacitance
Data Source
AI summary
A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line and the neighboring non-selected word line from the word line decoder, and applying a read voltage to the selected word line, a first voltage to non-selected word lines other than the neighboring non-selected word line, and a second voltage to the neighboring non-selected word line.