Flash Memory Address Mapping via Wordline-Embedded Metadata
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Solution Overview
Problem
As flash memory capacity increases and reading resolution becomes finer, the size of the logical-to-physical address map grows, making it impractical to store in RAM and leading to delays due to the need for larger or additional maps, especially when compression is implemented between logical and physical spaces.
Innovation Solution
A storage module where a single wordline stores information about multiple logical addresses, allowing fast access to compressed data without increasing the size of mapping tables, by storing the internal address within the wordline itself, reducing complexity and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity increases and reading resolution becomes finer, then the storage capability improves, but the size of the logical-to-physical address map grows larger making it impractical to store in RAM
Solution Approach 1:
The patent segments the address map information by storing only partial mapping information in RAM while keeping the complete address map in flash memory. The controller divides the address management into two parts: a compressed version in RAM for quick access and the full version in flash memory for completeness, thereby reducing RAM requirements while maintaining mapping functionality.
Solution Approach 2:
The patent implements a nested structure where the complete address map is stored in flash memory and a compressed/condensed version is nested within RAM. The controller maintains a simplified address map in RAM that references the more comprehensive map in flash memory, creating a nested information hierarchy that optimizes both speed and completeness.
2Measurement precision
If larger or additional logical-to-physical address maps are used to address compression, then the mapping accuracy improves, but the system complexity and delay increase
Solution Approach 1:
The patent segments the address mapping function into two parts: a compressed address map stored in RAM for fast access and the complete address map stored in flash memory for full accuracy. The controller intelligently switches between these two representations based on the operation required, thereby maintaining mapping precision without requiring the entire large address map to be present in RAM simultaneously.
Solution Approach 2:
The patent changes the parameter of address map representation by using compressed or condensed versions in RAM versus full versions in flash memory. The controller dynamically adjusts the level of detail in the address map based on operational needs, transforming the address map from a static large structure to a flexible multi-level representation that adapts to different access patterns.
3Loss of information
If larger or additional logical-to-physical address maps are used to address compression, then the mapping completeness improves, but the access delay increases due to reading from flash memory
Solution Approach 1:
The patent performs preliminary action by pre-loading essential address map information into RAM in a compressed format before it is needed for operations. The controller maintains this condensed address map in advance in RAM, so that when address translation is required, the information is already available in fast memory rather than requiring a time-consuming read from flash memory at the moment of access.
Solution Approach 2:
The patent applies local quality by storing different levels of address map detail in different memory locations optimized for their specific purposes. Frequently accessed or critical address mappings are kept in RAM in compressed form for fast access, while less frequently accessed or supplementary mapping information remains in flash memory, creating a spatially differentiated quality distribution that optimizes overall system performance.
Data Source
AI summary
A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory having a plurality of wordlines and a controller. The controller is configured to use a logical-to-physical address map to convert a logical address to a physical address of a wordline. A plurality of logical addresses in the map point to a single wordline, and the single wordline contains both data associated with the plurality of logical addresses and information about where to find each of the plurality of logical addresses in the single wordline . Storing the information about where to find each of the plurality of logical addresses in the wordline itself avoids the delay and complexity of using a larger logical-to-physical address map or multiple maps.