Flash Memory Wordline Critical Dimension Control via Trench Definition
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Solution Overview
Problem
Conventional flash memory array fabrication faces challenges in achieving uniform wordline width and increased parasitic current flow between wordlines, leading to reduced performance and reliability due to the scaling down of memory arrays.
Innovation Solution
The method involves forming trenches in a substrate to define wordline regions, depositing a dielectric layer, and creating an ONO stack over bitlines and wordlines, which reduces parasitic current and enhances wordline critical dimension uniformity by determining the active wordline width through the distance between trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lithographical patterning is used to determine wordline width in conventional flash memory fabrication, then the process is simple and direct, but wordline critical dimension uniformity deteriorates significantly as memory arrays are scaled down
Solution Approach 1:
The patent segments the wordline formation process into two independent stages: (1) forming trenches with uniform width to define wordline region boundaries, and (2) depositing polysilicon to form the actual wordlines. This segmentation allows the trench width (determining active wordline width) to be controlled separately from the polysilicon deposition, enabling precise control of wordline critical dimension while maintaining fabrication simplicity.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming trenches downward into the substrate to define wordline regions, rather than relying solely on lateral lithographical patterning. The trench depth and width provide an additional degree of freedom for controlling wordline dimensions, improving critical dimension uniformity as memory arrays are scaled down.
2Productivity
If memory arrays are scaled down to increase integration density, then productivity and capacity improve, but parasitic current flow between adjacent wordlines increases
Solution Approach 1:
The patent introduces dielectric material as an intermediary substance filling the trenches between adjacent wordline regions. This dielectric layer acts as an electrical insulator that blocks parasitic current flow between neighboring wordlines, enabling higher integration density without suffering from increased parasitic effects.
Solution Approach 2:
The patent extracts the problematic substrate material between wordlines by forming trenches and replacing it with dielectric material. This removal of conductive substrate material eliminates the parasitic current path, allowing memory arrays to be scaled down without the harmful parasitic effects.
3Volume of moving object
If ONO stack thickness is reduced to enable further scaling, then device size decreases, but parasitic current flow increases due to inverse proportionality
Solution Approach 1:
The patent introduces dielectric material as an intermediary barrier in the trenches between wordlines. This dielectric layer provides additional electrical isolation that compensates for the reduced ONO stack thickness, allowing the memory array to be scaled down while maintaining control over parasitic current flow through the separate trench-based isolation mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced parasitic current flow, improved wordline critical dimension uniformity, and increased scalability and yield of memory arrays by decoupling active and actual wordline widths, thereby enhancing memory array performance and reliability.
Implementation Method 1
depositing a dielectric layer
Implementation Method 2
creating an ONO stack over bitlines and wordlines
Data Source
AI summary
According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.