Flash Memory Write Algorithm for Dual-Bit Cell Pulse Control
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Solution Overview
Problem
In dual cell flash memory, existing write algorithms do not efficiently manage programming pulses for bits, leading to potential over-programming when both bits of a memory cell are being programmed, which affects storage density and reliability.
Innovation Solution
A memory controller determines whether both bits of a memory cell are being programmed and adjusts the duration of programming pulses, applying them for a reduced duration when both bits are being programmed, rather than the standard duration, to prevent over-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the standard write algorithm applies programming pulses for the standard duration to each bit, then the writing speed is improved, but over-programming occurs when both bits of a memory cell are being programmed, reducing reliability
Solution Approach 1:
The write algorithm dynamically adjusts the programming pulse duration based on the specific write operation being performed. When both bits of a dual cell are being programmed, the algorithm reduces the pulse duration to prevent over-programming, while maintaining standard duration for single-bit programming operations.
Solution Approach 2:
The invention changes the parameter of programming pulse duration from a fixed standard value to a variable value that depends on the write operation type. The controller determines whether to apply reduced duration or standard duration based on whether both bits are being programmed, thereby optimizing both speed and reliability.
2Reliability
If the programming pulse duration is reduced when both bits are being programmed, then over-programming is prevented and reliability is improved, but the write operation time increases
Solution Approach 1:
Instead of applying the full standard programming pulse duration in all cases, the algorithm applies a reduced duration only when necessary (when both bits are being programmed). This partial action approach prevents over-programming while minimizing the time penalty to the overall write operation.
3Quantity of substance
If dual cell flash memory stores two bits on opposite sides of a memory cell, then storage density is improved, but the complexity of managing programming pulses for each bit increases
Solution Approach 1:
The memory controller automatically determines whether both bits of a dual cell are being programmed and self-adjusts the programming pulse duration accordingly. This self-service mechanism eliminates the need for complex external control logic while maintaining high storage density.
Data Source
AI summary
A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the memory controller causes the application of each programming pulse to the bit to occur for a reduced duration. Otherwise, the memory controller causes the application of each programming pulse to the bit to occur for a standard duration. The reduced duration is less than three-fourths of the standard duration.