Flash Memory Multi-Level Cell Writing Method
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Solution Overview
Problem
Flash memory writing speed and service life are limited by the time-consuming process of erasing data, which reduces the overall performance and lifespan of the memory.
Innovation Solution
A method and control device that utilize a writing circuit and determining circuit to store bits in multi-level cells of a flash memory, reducing erasing times by writing data in stages, starting with lower bits and incrementing to higher bits, thereby minimizing full-load erasing and maximizing the service life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory control circuit erases data previously stored in the memory unit before writing new data, then the memory unit can be reused, but the data writing speed decreases due to additional erasing time
Solution Approach 1:
The patent segments the data writing process into multiple stages: first writing to lower bits, then to higher bits. This segmentation allows the system to avoid complete erasure operations while maintaining the ability to update memory units, thereby improving writing speed without sacrificing reliability
Solution Approach 2:
The patent performs preliminary actions by writing to lower bits first before proceeding to higher bits. This preliminary writing approach prepares the memory unit in a state that reduces the need for complete erasure, thus improving writing speed while maintaining reuse capability
2Productivity
If the flash memory performs more writing and erasing operations, then the data storage capacity is increased, but the service life of the flash memory decreases
Solution Approach 1:
By segmenting the writing process into lower bit and higher bit stages, the patent reduces the frequency of complete erasure operations. This segmentation allows more writing operations to be performed without proportionally increasing erasing operations, thereby increasing storage capacity while preserving service life
Solution Approach 2:
The patent changes the parameter of data representation by using multi-level cells that can store multiple bits. This parameter change allows the system to increase storage capacity through more efficient use of existing cells without requiring proportional increases in writing and erasing operations, thus protecting service life
Data Source
AI summary
A method for writing data into a flash memory, wherein the flash memory includes a plurality multi-level cells, and each of the plurality of multi-level cells is capable of storing a plurality of bits. The method includes: storing a first bit into each of the plurality of multi-level cells respectively; determining if each of the plurality of multi-level cells stores the first bit respectively; and when each of the plurality of multi-level cells stores the first bit respectively, storing a second bit into each of the plurality of multi-level cells respectively.