Flash Memory Writing Management via Even-Odd Data Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face inefficiencies in flash memory access control, particularly with multiple level cell (MLC) flash memories, which lead to increased buffer size requirements and potential side effects when adopting newer technologies, resulting in a trade-off between budget and performance.
Innovation Solution
A method and apparatus for writing management in memory devices that involves extracting even and odd page data, using confirmation commands to manage programming operations across internal buffers and blocks, allowing for optimal performance without significantly increasing costs or introducing side effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If newer flash memory technologies (MLC) are utilized to increase recording density and capacity, then storage ability and capacity are improved, but buffer size requirements double and stability issues arise
Solution Approach 1:
The patent segments the writing process into distinct phases: receiving data, extracting even and odd page data, writing to internal buffer, and final programming to NV memory. This segmentation allows the system to manage MLC's complex writing operations in controlled steps, reducing the required buffer size while maintaining high recording density.
Solution Approach 2:
The patent performs preliminary actions by extracting and preparing even and odd page data before the actual programming operation. Data is written to the internal buffer first, and only after proper management and confirmation commands are issued does the programming to NV memory elements occur. This preliminary preparation reduces the peak buffer size requirement.
2Quantity of substance
If newer flash memory technologies (MLC) are utilized to increase recording density and capacity, then storage ability and capacity are improved, but instability issues and access control problems arise
Solution Approach 1:
The patent implements feedback mechanisms through confirmation commands that trigger NV memory to execute programming operations only after data is properly prepared in the internal buffer. The controller receives feedback about the programming status and adjusts subsequent operations accordingly, ensuring stable access control despite MLC's inherent instability.
Solution Approach 2:
The patent introduces an intermediary internal buffer between the host device and NV memory elements. This buffer acts as a mediator that manages the complex writing operations of MLC flash memory, isolating the instability issues from the host system while maintaining reliable access control through structured command sequences.
3Productivity
If buffer size is increased to support MLC flash memory operations, then writing performance is improved, but cost increases
Solution Approach 1:
The patent applies partial action by writing only the necessary portions of data (even and odd page data separately) to the internal buffer at any given time, rather than requiring the entire dataset to be buffered simultaneously. This approach achieves adequate writing performance for MLC operations while keeping the buffer size and associated costs manageable.
Data Source
AI summary
A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.