Flash Mode Control for Non-Volatile Memory Data Integrity
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Solution Overview
Problem
In non-volatile memory cell arrays, such as PRAM, RRAM, and MRAM, data writing and erasing operations can result in incorrect readings due to the time required for phase change materials to stabilize in set or reset states, leading to potential data corruption before the material fully settles.
Innovation Solution
A semiconductor device with a control unit that generates mode signals to enable or disable flash mode, preventing erasure operations if flash mode is not enabled, and includes write circuits that selectively write or erase data based on these signals to ensure accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write or erase operations are performed on non-volatile memory cell arrays using phase change materials, then data storage capability is achieved, but data corruption occurs due to incomplete stabilization of the phase change material states
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation to detect whether the phase change material has fully stabilized. This pre-check mechanism prevents data corruption by identifying unstable states before attempting to write new data, thereby ensuring data accuracy without requiring extended stabilization time to be wasted
2Productivity
If erasure operations are performed without mode verification, then writing speed is improved, but data corruption occurs due to premature erasure before phase change material stabilization
Solution Approach 1:
The patent implements feedback control by reading the memory cell state before erasure and using this information to determine whether erasure should proceed. The system feeds back the stabilization status to control the erasure operation, ensuring that erasure only occurs when the phase change material is fully stabilized, thus maintaining data integrity while preserving write speed through intelligent operation control
3Reliability
If flash mode is always enabled to prevent data corruption, then data accuracy is improved, but device complexity increases due to additional mode control circuitry and signals
Solution Approach 1:
The patent applies local quality by implementing mode control at the memory block level rather than globally across the entire memory array. Different blocks can operate in different modes (flash mode or normal mode) based on their specific stabilization requirements, allowing the system to maintain high reliability where needed while minimizing the overhead of mode control circuitry in other areas, thus reducing overall device complexity
Data Source
AI summary
In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.