Flash Neural-Array Synapse Circuit for In-Memory AI Computing
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Solution Overview
Problem
Current neural network hardware accelerators face challenges in achieving high-performance compute operations while minimizing power consumption, which limits their application in energy-efficient artificial intelligence tasks.
Innovation Solution
The implementation of a neural circuit in a neural-array based flash memory system using single-level-cell (SLC) and many-level-cell (MLC) flash cells, where input vectors are translated into equivalent currents and threshold voltage levels, enabling efficient storage and computation of weight vectors in non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If CPU's and GPU's are used to implement neural network models in hardware, then compute operations can be performed, but power consumption is high
Solution Approach 1:
The patent replaces traditional CPU/GPU computational architectures with a neural network hardware accelerator that uses non-volatile memory cells (such as RRAM, PCM, or MRAM) to directly perform multiply-accumulate operations. This substitution eliminates the need for data movement between separate storage and compute units, significantly reducing power consumption while maintaining computational capability.
Solution Approach 2:
The neural network hardware accelerator is designed to perform multiple neural network operations (matrix multiplication, convolution, activation functions) using a unified architecture based on non-volatile memory cells. This multi-functional design reduces the overall power consumption compared to using specialized CPU or GPU cores for each operation type.
2Productivity
If traditional hardware accelerators are used for neural networks, then compute performance can be achieved, but energy efficiency is poor
Solution Approach 1:
The patent replaces von Neumann architecture with a memory-compute unified architecture where non-volatile memory cells perform analog multiply-accumulate operations directly. This eliminates the energy-intensive data transfer between memory and processor, achieving both high compute performance and superior energy efficiency simultaneously.
Solution Approach 2:
The patent changes the operational parameters by using analog resistance values in non-volatile memory cells to represent weight values, enabling parallel analog computation. This parameter change from digital to analog domain allows high-performance compute operations with significantly reduced energy consumption compared to traditional digital hardware accelerators.
3Use of energy by moving object
If non-volatile memory cells are used for neural network operations, then energy consumption is reduced, but implementation complexity increases
Solution Approach 1:
The patent divides the neural network hardware accelerator into modular blocks, each handling specific neural network layers or operations. This segmentation allows for standardized design and fabrication of non-volatile memory-based compute units, reducing overall implementation complexity through modularity and reuse of design patterns.
Solution Approach 2:
The patent introduces digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) as intermediary components that bridge the digital control logic and analog computation in non-volatile memory cells. These intermediaries simplify the interface between digital and analog domains, making the system more manageable despite the inherent complexity of analog memory computation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance neural network operations with significantly reduced energy consumption, expanding the applicability of neural networks in various AI applications.
Implementation Method 1
each weight vector is translated into an equivalent threshold voltage level to be stored in one of many SLC flash cells assigned to each synapse
Implementation Method 2
converting the N digital bits of the weight vector or synapse Yi into equivalent threshold voltage level
Implementation Method 3
each input vector is translated into an equivalent current IDACi
Data Source
AI summary
In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2N−1 single-level-cell (SLC) flash cells for each synapse (Yi) connected to a bit line forming a neuron. The method includes the step of providing an input vector (Xi) for each synapse Yi wherein each input vector is translated into an equivalent electrical signal ESi (current IDACi, pulse TPULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 20*ESi to (2N−1)*ESi. The method includes the step of providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Yi). The method includes the step of providing for 2N possible threshold voltage levels or resistance levels in the 2N−1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Yi into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Yi). The method includes the step of turning off all remaining 2N−1 flash cells of the respective synapse (Yi).Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Yi) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.