Flash Neural-Array Synapses Using Threshold-Stored Weights
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Solution Overview
Problem
Existing neural network hardware accelerators face challenges in achieving high-performance compute operations while minimizing power consumption.
Innovation Solution
Implementing a neural circuit using a neural-array based non-volatile memory, specifically flash memory, with single-level-cell (SLC) and many-level-cell (MLC) flash cells to store weight vectors as threshold voltage levels, enabling efficient conversion of digital bits into equivalent threshold voltage levels for synapses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If CPU's and GPU's are used to implement neural network models, then compute operations can be performed, but power consumption is high
Solution Approach 1:
The patent divides the neural network compute operations into separate functional blocks: input vector registration, weight vector storage in non-volatile memory, and output generation. This segmentation allows each block to be optimized independently, with weight storage using energy-efficient non-volatile memory while input processing uses conventional circuits.
Solution Approach 2:
The patent introduces non-volatile memory cells as an intermediary between weight storage and compute operations. These cells store weight vectors and provide analog-to-digital conversion capability, eliminating the need for continuous power supply to maintain weight states and reducing the energy required for weight access during inference.
2Productivity
If high-performance neural network hardware accelerators are implemented, then compute operations improve, but device complexity increases
Solution Approach 1:
The non-volatile memory cells serve multiple functions simultaneously: they store weight vectors, perform analog-to-digital conversion, and provide the computational substrate for neural network operations. This multi-functionality reduces the need for separate dedicated components, thereby simplifying the overall device architecture while maintaining high compute performance.
Solution Approach 2:
The patent merges the weight storage function and the compute function into a single integrated structure using non-volatile memory cells. Instead of having separate memory and processing units, the weight vectors are stored in and processed by the same non-volatile memory array, reducing inter-component communication overhead and simplifying the hardware architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances compute operations with low energy consumption, allowing for high-performance neural network applications.
Implementation Method 1
providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level to be stored in one of many SLC flash cells assigned to each synapse (Yi)
Data Source
AI summary
In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2N−1 single-level-cell (SLC) flash cells for each synapse (Yi) connected to a bit line forming a neuron. The method includes the step of providing an input vector (Xi) for each synapse Yi wherein each input vector is translated into an equivalent electrical signal ESi (current IDACi, pulse TPULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 20*ESi to (2N−1)*ESi. The method includes the step of providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Yi). The method includes the step of providing for 2N possible threshold voltage levels or resistance levels in the 2N−1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Yi into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Yi). The method includes the step of turning off all remaining 2N−1 flash cells of the respective synapse (Yi).Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Yi) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.