Integrated Flash Memory Oxide Layout for Nitridation Control
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Solution Overview
Problem
Integrating non-volatile memory (NVM) arrays with additional circuitry in the same integrated circuit (IC) poses challenges due to the complexity of controlling dielectric layers, particularly in the presence of nitridation, which affects the thickness and properties of these layers.
Innovation Solution
The solution involves forming a flash memory bit structure on a semiconductor substrate with a word line structure and a first oxide layer that is free of nitridation, and a transistor structure with a gate oxide layer that includes nitridation, allowing for independent control of dielectric layers and enabling modular processing with complementary metal-oxide-semiconductor (CMOS) processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a unified dielectric layer is used for both flash memory and transistor gate structures, then processing steps are simplified, but control over dielectric layer thickness and properties is compromised due to nitridation effects
Solution Approach 1:
The patent divides the dielectric layer into two separate structures: a first dielectric layer for the flash memory bit structure and a second dielectric layer for the transistor gate structure. This segmentation allows each dielectric layer to be independently formed and controlled, with the first layer being free of nitridation and the second layer receiving nitridation treatment, thereby resolving the contradiction between processing simplicity and thickness control precision.
Solution Approach 2:
The patent applies different treatments and properties to different regions: the first dielectric layer is specifically designed to be free of nitridation for flash memory, while the second dielectric layer is nitrided for transistor gate structures. This local differentiation of material properties allows each component to have optimal characteristics for its specific function while maintaining overall integration.
2Productivity
If integrated processing is used for flash memory and CMOS circuitry, then device density is increased, but design flexibility is reduced due to conflicting processing requirements
Solution Approach 1:
The patent segments the processing into distinct sequences for flash memory and transistor structures. The flash memory bit structure is formed first with its dielectric layer, then the transistor gate structure is formed separately with its own dielectric layer. This segmented processing approach maintains design flexibility by allowing independent optimization of each device type while achieving high device density through integration on the same substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for independent control of dielectric layer thickness and avoids nitridation issues, facilitating easier integration of flash memory with CMOS processing and enhancing the design flexibility and efficiency of the IC.
Implementation Method 1
The transistor structure includes a gate oxide layer including nitridation
Data Source
AI summary
The present disclosure generally relates to an integrated circuit (IC) including a flash memory bit structure. In an example, an IC includes a flash memory bit structure and a transistor structure. The flash memory bit structure is on a semiconductor substrate. The flash memory bit structure includes a word line structure and a first oxide layer disposed between the semiconductor substrate and the word line structure. The first oxide layer is free of nitridation. The transistor structure is on the semiconductor substrate. The transistor structure includes a gate structure and a gate oxide layer including nitridation. The gate oxide layer is over the semiconductor substrate. The gate structure is over the gate oxide layer.