Multi-bit Flash Page Buffer Circuit Adaptability
Solution Overview
Problem
Existing page buffer technology for flash memory devices is not adaptable to composite or multi-mode flash memory devices, requiring multiple page buffers based on the mode of operation, which increases chip size and complexity.
Innovation Solution
A flash memory device with a memory cell array comprising both m-bit and n-bit cells, a page buffer circuit capable of operating in programming, erasing, and reading operations for both types, and a control logic unit to determine the functions of page buffers based on the type of memory cells, allowing flexible operation without altering the page buffer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple page buffers are used to support different bit configurations, then adaptability to various memory cell types is improved, but device complexity and chip size increase
Solution Approach 1:
The page buffer circuit is designed with a universal structure that can handle both m-bit and n-bit memory cell configurations using the same hardware components. The control logic unit dynamically configures the page buffer's operation mode based on the memory cell type, allowing a single page buffer to perform multiple functions rather than requiring separate dedicated buffers for each configuration.
Solution Approach 2:
The page buffer circuit incorporates dynamic reconfiguration capability through the control logic unit, which adjusts the buffer's internal state and operation parameters based on the detected memory cell type. This dynamic adaptation allows the same hardware to flexibly switch between different bit configurations without physical reconfiguration or additional components.
2Adaptability or versatility
If multiple page buffers are used to support different bit configurations, then compatibility with various memory modes is improved, but manufacturing complexity increases
Solution Approach 1:
The invention employs a universal page buffer design that can be manufactured as a single standardized component. The control logic unit within the page buffer automatically detects and adapts to different memory cell configurations (m-bit or n-bit), eliminating the need to manufacture and stock multiple specialized buffer variants for different memory modes.
3Device complexity
If a single page buffer is used for both m-bit and n-bit cells, then device complexity is reduced, but the ability to perform specialized operations for different cell types deteriorates
Solution Approach 1:
The page buffer incorporates dynamic configuration capabilities through the control logic unit, which adjusts the buffer's internal parameters, timing sequences, and operation modes based on the detected memory cell type. This dynamic adaptation ensures that the single page buffer can perform specialized operations appropriate for each cell type (m-bit or n-bit) while maintaining a unified hardware structure.
Solution Approach 2:
The control logic unit modifies operational parameters of the page buffer such as timing sequences, voltage levels, and data width configurations based on the memory cell type. These parameter changes allow the same hardware structure to reliably perform specialized operations for different cell types by adapting its behavior rather than its physical structure.
Data Source
AI summary
A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit controls functions of the page buffers in accordance with the number of bits stored in corresponding memory cells.