Flash Memory Page Buffer Parameter Tuning for Noise Robustness
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Solution Overview
Problem
Miniaturization of flash memory cells and transistors makes them more susceptible to noise, affecting the reliability and accuracy of semiconductor devices.
Innovation Solution
An electronic device with a circuit design system that includes a processor and memory, which performs circuit simulations on a flash memory device with a page buffer, adjusts transistor and voltage parameters based on reward calculations to optimize performance and robustness against noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells and transistors are miniaturized to increase storage capacity, then storage density is improved, but noise susceptibility increases
Solution Approach 1:
The patent applies parameter changes by adjusting transistor dimensions (channel width W and length L), voltage levels (read voltage VRD, pass voltage VPD), and current thresholds to optimize the balance between storage density and noise immunity. The reinforcement learning system iteratively modifies these parameters to maximize noise robustness while maintaining miniaturization benefits.
Solution Approach 2:
The patent implements feedback through reinforcement learning where the system performs circuit simulations, evaluates noise susceptibility based on simulation results, and uses the evaluation (reward) to adjust parameters for subsequent simulations. This closed-loop feedback enables continuous optimization of the circuit design to achieve better noise immunity without sacrificing storage density.
2Quantity of substance
If transistor dimensions are reduced to increase integration, then manufacturing precision requirements increase
Solution Approach 1:
The patent uses parameter changes to compensate for manufacturing variations by adjusting operational parameters (voltages, currents, timing) based on simulated performance. The reinforcement learning system identifies optimal parameter combinations that maintain circuit functionality despite variations in physical transistor dimensions, effectively decoupling integration density from manufacturing precision requirements.
Solution Approach 2:
The patent applies dynamics by making the circuit parameters adaptive rather than fixed. The reinforcement learning process dynamically adjusts transistor dimensions, voltage levels, and timing parameters based on simulated noise conditions and performance metrics, enabling the design to accommodate manufacturing tolerances while maintaining optimal integration density.
3Reliability
If circuit parameters are optimized for noise resistance, then reliability is improved, but design complexity increases
Solution Approach 1:
The patent applies self-service through automated reinforcement learning that performs circuit simulations, evaluates performance, and adjusts parameters autonomously. The system serves itself by using its own computational resources to optimize the design, eliminating the need for manual iterative design processes and reducing overall design complexity despite the sophisticated optimization being performed.
Solution Approach 2:
The patent replaces manual mechanical design processes with computational automation. Instead of physically prototyping and testing circuits, the system uses computer-based reinforcement learning and circuit simulation to optimize parameters, substituting physical iteration with virtual optimization that achieves better reliability without proportionally increasing design complexity.
Data Source
AI summary
An operating method of a circuit design system which includes a processor and a memory includes reading, at the processor, a circuit layout of a flash memory device including a page buffer from the memory, initializing, at the processor, a value of a first parameter of at least one transistor of the page buffer and a value of a second parameter of at least one voltage applied to the page buffer, performing, at the processor, circuit simulation on the page buffer using the initialized first and second parameters, and calculating, at the processor, a reward based on a result of the circuit simulation. The processor is configured to perform, in response to the reward being not greater than a threshold value, a subsequent action. The subsequent action includes adjust the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage, and perform subsequent circuit simulation on the page buffer using the adjusted first and second parameters.