Flash Page Retirement Without Dummy Programming

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Solution Overview

Problem

Current NAND flash memory management schemes face challenges in efficiently retiring defective pages, leading to increased data maintenance and implementation complexity, particularly when using sub-block granularity, which results in undesirable NAND bandwidth consumption and performance non-uniformity.

Innovation Solution

Implementing a page retire feature with a NAND defect management scheme that retires pages with read errors at a page granularity, avoiding unnecessary dummy page programming and using shifted program verify voltages to maintain NAND bandwidth and enable fast read mode compatibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sub-block granularity is used for memory retirement, then memory endurance is improved, but data maintenance complexity and implementation complexity increase

Engineering Contradiction:
Improvememory enduranceVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory management unit into separate components: a defect management unit that handles retirement decisions, a mapping unit that tracks logical-to-physical page mappings, and a defect list data structure. This segmentation allows complex retirement operations to be distributed across multiple simpler components, reducing overall implementation complexity while maintaining sub-block granularity for improved endurance.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If page granularity retirement is implemented, then data maintenance is reduced, but NAND bandwidth consumption increases

Engineering Contradiction:
Improvedata maintenance amountVSAvoidNAND bandwidth consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent implements preliminary action by pre-programming dummy pages with dummy data before retiring physical pages. This preliminary programming ensures that when logical pages are remapped to physical pages, the data is already in place and can be read immediately, eliminating the need for subsequent bandwidth-intensive data transfer operations and reducing overall NAND bandwidth consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating dummy pages that replicate the structure and metadata of actual data pages without containing real data. These dummy pages are copied to replace retired physical pages in the mapping structure, allowing the system to maintain page-level granularity for data maintenance while avoiding the bandwidth cost of copying actual data during the retirement process.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If dummy pages are programmed for retired pages, then fast read mode compatibility is maintained, but NAND bandwidth is wasted

Engineering Contradiction:
Improvefast read mode compatibilityVSAvoidNAND bandwidth waste
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by selectively programming dummy pages only for specific physical pages that need to be retired, rather than uniformly treating all pages. The defect management unit identifies which physical pages contain defects and applies the dummy page programming strategy only to those local regions, maintaining fast read mode compatibility for affected areas while avoiding unnecessary bandwidth consumption in defect-free regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10437512B2Techniques for non-volatile memory page retirement
Publication Date: 2019.10.08 INTEL CORP
  • US10437512B2 patent drawing
  • US10437512B2 patent drawing
  • US10437512B2 patent drawing

AI summary

Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.